[libcamera-devel] [PATCH 1/2] include: linux: Update Linux headers to v5.12-rc1
Kieran Bingham
kieran.bingham at ideasonboard.com
Wed Mar 3 17:31:50 CET 2021
Hi Laurent,
On 02/03/2021 20:16, Laurent Pinchart wrote:
> Update Linux headers to v5.12-rc1, to provide the
> MEDIA_ENT_F_PROC_VIDEO_ISP entity function.
>
> The DRM FourCC and modifiers that were manually added in commits
> 9db0ed5e2065, 38f2efb05cef and 90c793c6989f are kept. New Intel DRM
> format modifiers are conflicting with IPU3_FORMAT_MOD_PACKED, which is
> updated as a result.
>
> The V4L2 controls and formats that were manually added in commit
> 43d81d43fe91 are kept. This causes a conflict in the V4L2 control base
> for V4L2_CID_USER_BCM2835_ISP_BASE that needs to be resolved in the
> downstream Raspberry Pi kernel first.
>
> The intel-ipu3.h header is manually exported with the
> scripts/headers_install.sh script. The script complained about a missing
> "WITH Linux-syscall-note" license extension, which has been worked
> around manually. The issue has been reported upstream in [1].
>
> [1] https://lore.kernel.org/linux-media/20210207235610.15687-1-laurent.pinchart@ideasonboard.com/T/#u
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
That's a lot of churn, so it's hard to review precisely. Perhaps we
should try to do this every kernel release to minimise the changes.
Acked-by: Kieran Bingham <kieran.bingham at ideasonboard.com>
> ---
> include/linux/dma-heap.h | 6 +-
> include/linux/drm_fourcc.h | 530 +++++++++++++++++-
> include/linux/intel-ipu3.h | 22 +-
> include/linux/media-bus-format.h | 14 +-
> include/linux/media.h | 1 +
> include/linux/rkisp1-config.h | 92 +++-
> include/linux/v4l2-controls.h | 916 ++++++++++++++++++++++++-------
> include/linux/v4l2-mediabus.h | 15 +-
> include/linux/v4l2-subdev.h | 26 +-
> include/linux/videodev2.h | 99 +++-
> 10 files changed, 1444 insertions(+), 277 deletions(-)
>
> diff --git a/include/linux/dma-heap.h b/include/linux/dma-heap.h
> index 6f84fa08e074..96b90cf0f8f7 100644
> --- a/include/linux/dma-heap.h
> +++ b/include/linux/dma-heap.h
> @@ -5,8 +5,8 @@
> * Copyright (C) 2011 Google, Inc.
> * Copyright (C) 2019 Linaro Ltd.
> */
> -#ifndef _UAPI_LINUX_DMABUF_POOL_H
> -#define _UAPI_LINUX_DMABUF_POOL_H
> +#ifndef _LINUX_DMABUF_POOL_H
> +#define _LINUX_DMABUF_POOL_H
>
> #include <linux/ioctl.h>
> #include <linux/types.h>
> @@ -50,4 +50,4 @@ struct dma_heap_allocation_data {
> #define DMA_HEAP_IOCTL_ALLOC _IOWR(DMA_HEAP_IOC_MAGIC, 0x0,\
> struct dma_heap_allocation_data)
>
> -#endif /* _UAPI_LINUX_DMABUF_POOL_H */
> +#endif /* _LINUX_DMABUF_POOL_H */
> diff --git a/include/linux/drm_fourcc.h b/include/linux/drm_fourcc.h
> index 72453692bdef..05d697ff30ce 100644
> --- a/include/linux/drm_fourcc.h
> +++ b/include/linux/drm_fourcc.h
> @@ -58,6 +58,30 @@ extern "C" {
> * may preserve meaning - such as number of planes - from the fourcc code,
> * whereas others may not.
> *
> + * Modifiers must uniquely encode buffer layout. In other words, a buffer must
> + * match only a single modifier. A modifier must not be a subset of layouts of
> + * another modifier. For instance, it's incorrect to encode pitch alignment in
> + * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
> + * aligned modifier. That said, modifiers can have implicit minimal
> + * requirements.
> + *
> + * For modifiers where the combination of fourcc code and modifier can alias,
> + * a canonical pair needs to be defined and used by all drivers. Preferred
> + * combinations are also encouraged where all combinations might lead to
> + * confusion and unnecessarily reduced interoperability. An example for the
> + * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
> + *
> + * There are two kinds of modifier users:
> + *
> + * - Kernel and user-space drivers: for drivers it's important that modifiers
> + * don't alias, otherwise two drivers might support the same format but use
> + * different aliases, preventing them from sharing buffers in an efficient
> + * format.
> + * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
> + * see modifiers as opaque tokens they can check for equality and intersect.
> + * These users musn't need to know to reason about the modifier value
> + * (i.e. they are not expected to extract information out of the modifier).
> + *
> * Vendors should document their modifier usage in as much detail as
> * possible, to ensure maximum compatibility across devices, drivers and
> * applications.
> @@ -69,7 +93,7 @@ extern "C" {
> #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
> ((__u32)(c) << 16) | ((__u32)(d) << 24))
>
> -#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
> +#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
>
> /* Reserve 0 for the invalid format specifier */
> #define DRM_FORMAT_INVALID 0
> @@ -155,6 +179,12 @@ extern "C" {
> #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
> #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
>
> +/*
> + * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
> + * of unused padding per component:
> + */
> +#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
> +
> /* packed YCbCr */
> #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
> #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
> @@ -236,6 +266,12 @@ extern "C" {
> #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
> #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
> +/*
> + * 2 plane YCbCr
> + * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
> + * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
> + */
> +#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
>
> /*
> * 2 plane YCbCr MSB aligned
> @@ -265,6 +301,22 @@ extern "C" {
> */
> #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
>
> +/* 3 plane non-subsampled (444) YCbCr
> + * 16 bits per component, but only 10 bits are used and 6 bits are padded
> + * index 0: Y plane, [15:0] Y:x [10:6] little endian
> + * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
> + * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
> + */
> +#define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
> +
> +/* 3 plane non-subsampled (444) YCrCb
> + * 16 bits per component, but only 10 bits are used and 6 bits are padded
> + * index 0: Y plane, [15:0] Y:x [10:6] little endian
> + * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
> + * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
> + */
> +#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
> +
> /*
> * 3 plane YCbCr
> * index 0: Y plane, [7:0] Y
> @@ -362,7 +414,6 @@ extern "C" {
> */
>
> /* Vendor Ids: */
> -#define DRM_FORMAT_MOD_NONE 0
> #define DRM_FORMAT_MOD_VENDOR_NONE 0
> #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
> #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
> @@ -373,7 +424,8 @@ extern "C" {
> #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
> #define DRM_FORMAT_MOD_VENDOR_ARM 0x08
> #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
> -#define DRM_FORMAT_MOD_VENDOR_MIPI 0x0a
> +#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
> +#define DRM_FORMAT_MOD_VENDOR_MIPI 0x0b
>
> /* add more to the end as needed */
>
> @@ -388,8 +440,33 @@ extern "C" {
> * When adding a new token please document the layout with a code comment,
> * similar to the fourcc codes above. drm_fourcc.h is considered the
> * authoritative source for all of these.
> + *
> + * Generic modifier names:
> + *
> + * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
> + * for layouts which are common across multiple vendors. To preserve
> + * compatibility, in cases where a vendor-specific definition already exists and
> + * a generic name for it is desired, the common name is a purely symbolic alias
> + * and must use the same numerical value as the original definition.
> + *
> + * Note that generic names should only be used for modifiers which describe
> + * generic layouts (such as pixel re-ordering), which may have
> + * independently-developed support across multiple vendors.
> + *
> + * In future cases where a generic layout is identified before merging with a
> + * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
> + * 'NONE' could be considered. This should only be for obvious, exceptional
> + * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
> + * apply to a single vendor.
> + *
> + * Generic names should not be used for cases where multiple hardware vendors
> + * have implementations of the same standardised compression scheme (such as
> + * AFBC). In those cases, all implementations should use the same format
> + * modifier(s), reflecting the vendor of the standard.
> */
>
> +#define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
> +
> /*
> * Invalid Modifier
> *
> @@ -409,6 +486,16 @@ extern "C" {
> */
> #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
>
> +/*
> + * Deprecated: use DRM_FORMAT_MOD_LINEAR instead
> + *
> + * The "none" format modifier doesn't actually mean that the modifier is
> + * implicit, instead it means that the layout is linear. Whether modifiers are
> + * used is out-of-band information carried in an API-specific way (e.g. in a
> + * flag for drm_mode_fb_cmd2).
> + */
> +#define DRM_FORMAT_MOD_NONE 0
> +
> /* Intel framebuffer modifiers */
>
> /*
> @@ -419,9 +506,12 @@ extern "C" {
> * a platform-dependent stride. On top of that the memory can apply
> * platform-depending swizzling of some higher address bits into bit6.
> *
> - * This format is highly platforms specific and not useful for cross-driver
> - * sharing. It exists since on a given platform it does uniquely identify the
> - * layout in a simple way for i915-specific userspace.
> + * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
> + * On earlier platforms the is highly platforms specific and not useful for
> + * cross-driver sharing. It exists since on a given platform it does uniquely
> + * identify the layout in a simple way for i915-specific userspace, which
> + * facilitated conversion of userspace to modifiers. Additionally the exact
> + * format on some really old platforms is not known.
> */
> #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
>
> @@ -434,9 +524,12 @@ extern "C" {
> * memory can apply platform-depending swizzling of some higher address bits
> * into bit6.
> *
> - * This format is highly platforms specific and not useful for cross-driver
> - * sharing. It exists since on a given platform it does uniquely identify the
> - * layout in a simple way for i915-specific userspace.
> + * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
> + * On earlier platforms the is highly platforms specific and not useful for
> + * cross-driver sharing. It exists since on a given platform it does uniquely
> + * identify the layout in a simple way for i915-specific userspace, which
> + * facilitated conversion of userspace to modifiers. Additionally the exact
> + * format on some really old platforms is not known.
> */
> #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
>
> @@ -475,6 +568,49 @@ extern "C" {
> #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
> #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
>
> +/*
> + * Intel color control surfaces (CCS) for Gen-12 render compression.
> + *
> + * The main surface is Y-tiled and at plane index 0, the CCS is linear and
> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
> + * main surface. In other words, 4 bits in CCS map to a main surface cache
> + * line pair. The main surface pitch is required to be a multiple of four
> + * Y-tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
> +
> +/*
> + * Intel color control surfaces (CCS) for Gen-12 media compression
> + *
> + * The main surface is Y-tiled and at plane index 0, the CCS is linear and
> + * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
> + * main surface. In other words, 4 bits in CCS map to a main surface cache
> + * line pair. The main surface pitch is required to be a multiple of four
> + * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
> + * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
> + * planes 2 and 3 for the respective CCS.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
> +
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
> + * compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
> + * and at index 1. The clear color is stored at index 2, and the pitch should
> + * be ignored. The clear color structure is 256 bits. The first 128 bits
> + * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
> + * by 32 bits. The raw clear color is consumed by the 3d engine and generates
> + * the converted clear color of size 64 bits. The first 32 bits store the Lower
> + * Converted Clear Color value and the next 32 bits store the Higher Converted
> + * Clear Color value when applicable. The Converted Clear Color values are
> + * consumed by the DE. The last 64 bits are used to store Color Discard Enable
> + * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
> + * corresponds to an area of 4x1 tiles in the main surface. The main surface
> + * pitch is required to be a multiple of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +
> /*
> * IPU3 Bayer packing layout
> *
> @@ -483,7 +619,7 @@ extern "C" {
> * the 6 most significant bits in the last byte unused. The format is little
> * endian.
> */
> -#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 8)
> +#define IPU3_FORMAT_MOD_PACKED fourcc_mod_code(INTEL, 9)
>
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> @@ -572,7 +708,113 @@ extern "C" {
> #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
>
> /*
> - * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
> + * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
> + * and Tegra GPUs starting with Tegra K1.
> + *
> + * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
> + * based on the architecture generation. GOBs themselves are then arranged in
> + * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
> + * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
> + * a block depth or height of "4").
> + *
> + * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
> + * in full detail.
> + *
> + * Macro
> + * Bits Param Description
> + * ---- ----- -----------------------------------------------------------------
> + *
> + * 3:0 h log2(height) of each block, in GOBs. Placed here for
> + * compatibility with the existing
> + * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
> + *
> + * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
> + * compatibility with the existing
> + * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
> + *
> + * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
> + * size). Must be zero.
> + *
> + * Note there is no log2(width) parameter. Some portions of the
> + * hardware support a block width of two gobs, but it is impractical
> + * to use due to lack of support elsewhere, and has no known
> + * benefits.
> + *
> + * 11:9 - Reserved (To support 2D-array textures with variable array stride
> + * in blocks, specified via log2(tile width in blocks)). Must be
> + * zero.
> + *
> + * 19:12 k Page Kind. This value directly maps to a field in the page
> + * tables of all GPUs >= NV50. It affects the exact layout of bits
> + * in memory and can be derived from the tuple
> + *
> + * (format, GPU model, compression type, samples per pixel)
> + *
> + * Where compression type is defined below. If GPU model were
> + * implied by the format modifier, format, or memory buffer, page
> + * kind would not need to be included in the modifier itself, but
> + * since the modifier should define the layout of the associated
> + * memory buffer independent from any device or other context, it
> + * must be included here.
> + *
> + * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
> + * starting with Fermi GPUs. Additionally, the mapping between page
> + * kind and bit layout has changed at various points.
> + *
> + * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
> + * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
> + * 2 = Gob Height 8, Turing+ Page Kind mapping
> + * 3 = Reserved for future use.
> + *
> + * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
> + * bit remapping step that occurs at an even lower level than the
> + * page kind and block linear swizzles. This causes the layout of
> + * surfaces mapped in those SOC's GPUs to be incompatible with the
> + * equivalent mapping on other GPUs in the same system.
> + *
> + * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
> + * 1 = Desktop GPU and Tegra Xavier+ Layout
> + *
> + * 25:23 c Lossless Framebuffer Compression type.
> + *
> + * 0 = none
> + * 1 = ROP/3D, layout 1, exact compression format implied by Page
> + * Kind field
> + * 2 = ROP/3D, layout 2, exact compression format implied by Page
> + * Kind field
> + * 3 = CDE horizontal
> + * 4 = CDE vertical
> + * 5 = Reserved for future use
> + * 6 = Reserved for future use
> + * 7 = Reserved for future use
> + *
> + * 55:25 - Reserved for future use. Must be zero.
> + */
> +#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
> + fourcc_mod_code(NVIDIA, (0x10 | \
> + ((h) & 0xf) | \
> + (((k) & 0xff) << 12) | \
> + (((g) & 0x3) << 20) | \
> + (((s) & 0x1) << 22) | \
> + (((c) & 0x7) << 23)))
> +
> +/* To grandfather in prior block linear format modifiers to the above layout,
> + * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
> + * with block-linear layouts, is remapped within drivers to the value 0xfe,
> + * which corresponds to the "generic" kind used for simple single-sample
> + * uncompressed color formats on Fermi - Volta GPUs.
> + */
> +static __inline__ __u64
> +drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
> +{
> + if (!(modifier & 0x10) || (modifier & (0xff << 12)))
> + return modifier;
> + else
> + return modifier | (0xfe << 12);
> +}
> +
> +/*
> + * 16Bx2 Block Linear layout, used by Tegra K1 and later
> *
> * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
> * vertically by a power of 2 (1 to 32 GOBs) to form a block.
> @@ -593,20 +835,20 @@ extern "C" {
> * in full detail.
> */
> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
> - fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
> + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
>
> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
> - fourcc_mod_code(NVIDIA, 0x10)
> + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
> - fourcc_mod_code(NVIDIA, 0x11)
> + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
> - fourcc_mod_code(NVIDIA, 0x12)
> + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
> - fourcc_mod_code(NVIDIA, 0x13)
> + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
> - fourcc_mod_code(NVIDIA, 0x14)
> + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
> #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
> - fourcc_mod_code(NVIDIA, 0x15)
> + DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
>
> /*
> * Some Broadcom modifiers take parameters, for example the number of
> @@ -723,7 +965,21 @@ extern "C" {
> * Further information on the use of AFBC modifiers can be found in
> * Documentation/gpu/afbc.rst
> */
> -#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
> +
> +/*
> + * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
> + * modifiers) denote the category for modifiers. Currently we have only two
> + * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
> + * different categories.
> + */
> +#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
> + fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
> +
> +#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
> +#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
> +
> +#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
> + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
>
> /*
> * AFBC superblock size
> @@ -817,6 +1073,28 @@ extern "C" {
> */
> #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
>
> +/* AFBC uncompressed storage mode
> + *
> + * Indicates that the buffer is using AFBC uncompressed storage mode.
> + * In this mode all superblock payloads in the buffer use the uncompressed
> + * storage mode, which is usually only used for data which cannot be compressed.
> + * The buffer layout is the same as for AFBC buffers without USM set, this only
> + * affects the storage mode of the individual superblocks. Note that even a
> + * buffer without USM set may use uncompressed storage mode for some or all
> + * superblocks, USM just guarantees it for all.
> + */
> +#define AFBC_FORMAT_MOD_USM (1ULL << 12)
> +
> +/*
> + * Arm 16x16 Block U-Interleaved modifier
> + *
> + * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
> + * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
> + * in the block are reordered.
> + */
> +#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
> + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
> +
> /*
> * Allwinner tiled modifier
> *
> @@ -831,6 +1109,220 @@ extern "C" {
> */
> #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
>
> +/*
> + * Amlogic Video Framebuffer Compression modifiers
> + *
> + * Amlogic uses a proprietary lossless image compression protocol and format
> + * for their hardware video codec accelerators, either video decoders or
> + * video input encoders.
> + *
> + * It considerably reduces memory bandwidth while writing and reading
> + * frames in memory.
> + *
> + * The underlying storage is considered to be 3 components, 8bit or 10-bit
> + * per component YCbCr 420, single plane :
> + * - DRM_FORMAT_YUV420_8BIT
> + * - DRM_FORMAT_YUV420_10BIT
> + *
> + * The first 8 bits of the mode defines the layout, then the following 8 bits
> + * defines the options changing the layout.
> + *
> + * Not all combinations are valid, and different SoCs may support different
> + * combinations of layout and options.
> + */
> +#define __fourcc_mod_amlogic_layout_mask 0xff
> +#define __fourcc_mod_amlogic_options_shift 8
> +#define __fourcc_mod_amlogic_options_mask 0xff
> +
> +#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
> + fourcc_mod_code(AMLOGIC, \
> + ((__layout) & __fourcc_mod_amlogic_layout_mask) | \
> + (((__options) & __fourcc_mod_amlogic_options_mask) \
> + << __fourcc_mod_amlogic_options_shift))
> +
> +/* Amlogic FBC Layouts */
> +
> +/*
> + * Amlogic FBC Basic Layout
> + *
> + * The basic layout is composed of:
> + * - a body content organized in 64x32 superblocks with 4096 bytes per
> + * superblock in default mode.
> + * - a 32 bytes per 128x64 header block
> + *
> + * This layout is transferrable between Amlogic SoCs supporting this modifier.
> + */
> +#define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
> +
> +/*
> + * Amlogic FBC Scatter Memory layout
> + *
> + * Indicates the header contains IOMMU references to the compressed
> + * frames content to optimize memory access and layout.
> + *
> + * In this mode, only the header memory address is needed, thus the
> + * content memory organization is tied to the current producer
> + * execution and cannot be saved/dumped neither transferrable between
> + * Amlogic SoCs supporting this modifier.
> + *
> + * Due to the nature of the layout, these buffers are not expected to
> + * be accessible by the user-space clients, but only accessible by the
> + * hardware producers and consumers.
> + *
> + * The user-space clients should expect a failure while trying to mmap
> + * the DMA-BUF handle returned by the producer.
> + */
> +#define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
> +
> +/* Amlogic FBC Layout Options Bit Mask */
> +
> +/*
> + * Amlogic FBC Memory Saving mode
> + *
> + * Indicates the storage is packed when pixel size is multiple of word
> + * boudaries, i.e. 8bit should be stored in this mode to save allocation
> + * memory.
> + *
> + * This mode reduces body layout to 3072 bytes per 64x32 superblock with
> + * the basic layout and 3200 bytes per 64x32 superblock combined with
> + * the scatter layout.
> + */
> +#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
> +
> +/*
> + * AMD modifiers
> + *
> + * Memory layout:
> + *
> + * without DCC:
> + * - main surface
> + *
> + * with DCC & without DCC_RETILE:
> + * - main surface in plane 0
> + * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
> + *
> + * with DCC & DCC_RETILE:
> + * - main surface in plane 0
> + * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
> + * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
> + *
> + * For multi-plane formats the above surfaces get merged into one plane for
> + * each format plane, based on the required alignment only.
> + *
> + * Bits Parameter Notes
> + * ----- ------------------------ ---------------------------------------------
> + *
> + * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_*
> + * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
> + * 13 DCC
> + * 14 DCC_RETILE
> + * 15 DCC_PIPE_ALIGN
> + * 16 DCC_INDEPENDENT_64B
> + * 17 DCC_INDEPENDENT_128B
> + * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
> + * 20 DCC_CONSTANT_ENCODE
> + * 23:21 PIPE_XOR_BITS Only for some chips
> + * 26:24 BANK_XOR_BITS Only for some chips
> + * 29:27 PACKERS Only for some chips
> + * 32:30 RB Only for some chips
> + * 35:33 PIPE Only for some chips
> + * 55:36 - Reserved for future use, must be zero
> + */
> +#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
> +
> +#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
> +
> +/* Reserve 0 for GFX8 and older */
> +#define AMD_FMT_MOD_TILE_VER_GFX9 1
> +#define AMD_FMT_MOD_TILE_VER_GFX10 2
> +#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
> +
> +/*
> + * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
> + * version.
> + */
> +#define AMD_FMT_MOD_TILE_GFX9_64K_S 9
> +
> +/*
> + * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
> + * GFX9 as canonical version.
> + */
> +#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
> +#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
> +#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
> +#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
> +
> +#define AMD_FMT_MOD_DCC_BLOCK_64B 0
> +#define AMD_FMT_MOD_DCC_BLOCK_128B 1
> +#define AMD_FMT_MOD_DCC_BLOCK_256B 2
> +
> +#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
> +#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
> +#define AMD_FMT_MOD_TILE_SHIFT 8
> +#define AMD_FMT_MOD_TILE_MASK 0x1F
> +
> +/* Whether DCC compression is enabled. */
> +#define AMD_FMT_MOD_DCC_SHIFT 13
> +#define AMD_FMT_MOD_DCC_MASK 0x1
> +
> +/*
> + * Whether to include two DCC surfaces, one which is rb & pipe aligned, and
> + * one which is not-aligned.
> + */
> +#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
> +#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
> +
> +/* Only set if DCC_RETILE = false */
> +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
> +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
> +
> +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
> +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
> +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
> +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
> +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
> +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
> +
> +/*
> + * DCC supports embedding some clear colors directly in the DCC surface.
> + * However, on older GPUs the rendering HW ignores the embedded clear color
> + * and prefers the driver provided color. This necessitates doing a fastclear
> + * eliminate operation before a process transfers control.
> + *
> + * If this bit is set that means the fastclear eliminate is not needed for these
> + * embeddable colors.
> + */
> +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
> +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
> +
> +/*
> + * The below fields are for accounting for per GPU differences. These are only
> + * relevant for GFX9 and later and if the tile field is *_X/_T.
> + *
> + * PIPE_XOR_BITS = always needed
> + * BANK_XOR_BITS = only for TILE_VER_GFX9
> + * PACKERS = only for TILE_VER_GFX10_RBPLUS
> + * RB = only for TILE_VER_GFX9 & DCC
> + * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
> + */
> +#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
> +#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
> +#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
> +#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
> +#define AMD_FMT_MOD_PACKERS_SHIFT 27
> +#define AMD_FMT_MOD_PACKERS_MASK 0x7
> +#define AMD_FMT_MOD_RB_SHIFT 30
> +#define AMD_FMT_MOD_RB_MASK 0x7
> +#define AMD_FMT_MOD_PIPE_SHIFT 33
> +#define AMD_FMT_MOD_PIPE_MASK 0x7
> +
> +#define AMD_FMT_MOD_SET(field, value) \
> + ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
> +#define AMD_FMT_MOD_GET(field, value) \
> + (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
> +#define AMD_FMT_MOD_CLEAR(field) \
> + (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
> +
> /* Mobile Industry Processor Interface (MIPI) modifiers */
>
> /*
> diff --git a/include/linux/intel-ipu3.h b/include/linux/intel-ipu3.h
> index 8ed1632164fd..ee0e6d0e4b2c 100644
> --- a/include/linux/intel-ipu3.h
> +++ b/include/linux/intel-ipu3.h
> @@ -120,13 +120,13 @@ struct ipu3_uapi_awb_config {
> #define IPU3_UAPI_AE_WEIGHTS 96
>
> /**
> - + * struct ipu3_uapi_ae_raw_buffer - AE global weighted histogram
> - + *
> - + * @vals: Sum of IPU3_UAPI_AE_COLORS in cell
> - + *
> - + * Each histogram contains IPU3_UAPI_AE_BINS bins. Each bin has 24 bit unsigned
> - + * for counting the number of the pixel.
> - + */
> + * struct ipu3_uapi_ae_raw_buffer - AE global weighted histogram
> + *
> + * @vals: Sum of IPU3_UAPI_AE_COLORS in cell
> + *
> + * Each histogram contains IPU3_UAPI_AE_BINS bins. Each bin has 24 bit unsigned
> + * for counting the number of the pixel.
> + */
> struct ipu3_uapi_ae_raw_buffer {
> __u32 vals[IPU3_UAPI_AE_BINS * IPU3_UAPI_AE_COLORS];
> } __attribute__((packed));
> @@ -418,7 +418,7 @@ struct ipu3_uapi_af_config_s {
> IPU3_UAPI_AWB_FR_SPARE_FOR_BUBBLES) * IPU3_UAPI_MAX_STRIPES)
>
> /**
> - * struct ipu3_uapi_awb_fr_meta_data - AWB filter response meta data
> + * struct ipu3_uapi_awb_fr_raw_buffer - AWB filter response meta data
> *
> * @meta_data: Statistics output on the grid after convolving with 1D filter.
> */
> @@ -1506,7 +1506,7 @@ struct ipu3_uapi_sharp_cfg {
> } __attribute__((packed));
>
> /**
> - * struct struct ipu3_uapi_far_w - Sharpening config for far sub-group
> + * struct ipu3_uapi_far_w - Sharpening config for far sub-group
> *
> * @dir_shrp: Weight of wide direct sharpening, u1.6, range [0, 64], default 64.
> * @reserved0: reserved
> @@ -1526,7 +1526,7 @@ struct ipu3_uapi_far_w {
> } __attribute__((packed));
>
> /**
> - * struct struct ipu3_uapi_unsharp_cfg - Unsharp config
> + * struct ipu3_uapi_unsharp_cfg - Unsharp config
> *
> * @unsharp_weight: Unsharp mask blending weight.
> * u1.6, range [0, 64], default 16.
> @@ -1772,7 +1772,7 @@ struct ipu3_uapi_vss_lut_y {
> } __attribute__((packed));
>
> /**
> - * struct ipu3_uapi_yuvp1_iefd_vssnlm_cf - IEFd Vssnlm Lookup table
> + * struct ipu3_uapi_yuvp1_iefd_vssnlm_cfg - IEFd Vssnlm Lookup table
> *
> * @vss_lut_x: vss lookup table. See &ipu3_uapi_vss_lut_x description
> * @vss_lut_y: vss lookup table. See &ipu3_uapi_vss_lut_y description
> diff --git a/include/linux/media-bus-format.h b/include/linux/media-bus-format.h
> index 16c1fa2d89a4..0dfc11ee243a 100644
> --- a/include/linux/media-bus-format.h
> +++ b/include/linux/media-bus-format.h
> @@ -34,7 +34,7 @@
>
> #define MEDIA_BUS_FMT_FIXED 0x0001
>
> -/* RGB - next is 0x101d */
> +/* RGB - next is 0x101e */
> #define MEDIA_BUS_FMT_RGB444_1X12 0x1016
> #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
> #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
> @@ -56,6 +56,7 @@
> #define MEDIA_BUS_FMT_RGB888_2X12_BE 0x100b
> #define MEDIA_BUS_FMT_RGB888_2X12_LE 0x100c
> #define MEDIA_BUS_FMT_RGB888_3X8 0x101c
> +#define MEDIA_BUS_FMT_RGB888_3X8_DELTA 0x101d
> #define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011
> #define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012
> #define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
> @@ -64,7 +65,7 @@
> #define MEDIA_BUS_FMT_RGB121212_1X36 0x1019
> #define MEDIA_BUS_FMT_RGB161616_1X48 0x101a
>
> -/* YUV (including grey) - next is 0x202d */
> +/* YUV (including grey) - next is 0x202e */
> #define MEDIA_BUS_FMT_Y8_1X8 0x2001
> #define MEDIA_BUS_FMT_UV8_1X8 0x2015
> #define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002
> @@ -86,6 +87,7 @@
> #define MEDIA_BUS_FMT_VYUY12_2X12 0x201d
> #define MEDIA_BUS_FMT_YUYV12_2X12 0x201e
> #define MEDIA_BUS_FMT_YVYU12_2X12 0x201f
> +#define MEDIA_BUS_FMT_Y14_1X14 0x202d
> #define MEDIA_BUS_FMT_UYVY8_1X16 0x200f
> #define MEDIA_BUS_FMT_VYUY8_1X16 0x2010
> #define MEDIA_BUS_FMT_YUYV8_1X16 0x2011
> @@ -155,4 +157,12 @@
> /* HSV - next is 0x6002 */
> #define MEDIA_BUS_FMT_AHSV8888_1X32 0x6001
>
> +/*
> + * This format should be used when the same driver handles
> + * both sides of the link and the bus format is a fixed
> + * metadata format that is not configurable from userspace.
> + * Width and height will be set to 0 for this format.
> + */
> +#define MEDIA_BUS_FMT_METADATA_FIXED 0x7001
> +
> #endif /* __LINUX_MEDIA_BUS_FORMAT_H */
> diff --git a/include/linux/media.h b/include/linux/media.h
> index f4ba8ae3e410..17432318a07e 100644
> --- a/include/linux/media.h
> +++ b/include/linux/media.h
> @@ -125,6 +125,7 @@ struct media_device_info {
> #define MEDIA_ENT_F_PROC_VIDEO_STATISTICS (MEDIA_ENT_F_BASE + 0x4006)
> #define MEDIA_ENT_F_PROC_VIDEO_ENCODER (MEDIA_ENT_F_BASE + 0x4007)
> #define MEDIA_ENT_F_PROC_VIDEO_DECODER (MEDIA_ENT_F_BASE + 0x4008)
> +#define MEDIA_ENT_F_PROC_VIDEO_ISP (MEDIA_ENT_F_BASE + 0x4009)
>
> /*
> * Switch and bridge entity functions
> diff --git a/include/linux/rkisp1-config.h b/include/linux/rkisp1-config.h
> index 9c24867ddd68..1b14c2303121 100644
> --- a/include/linux/rkisp1-config.h
> +++ b/include/linux/rkisp1-config.h
> @@ -1,4 +1,4 @@
> -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) */
> /*
> * Rockchip ISP1 userspace API
> * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> @@ -9,10 +9,6 @@
>
> #include <linux/types.h>
>
> -/* Vendor specific - used for RK_ISP1 camera sub-system */
> -#define V4L2_META_FMT_RK_ISP1_PARAMS v4l2_fourcc('R', 'K', '1', 'P') /* Rockchip ISP1 params */
> -#define V4L2_META_FMT_RK_ISP1_STAT_3A v4l2_fourcc('R', 'K', '1', 'S') /* Rockchip ISP1 3A statistics */
> -
> /* Defect Pixel Cluster Detection */
> #define RKISP1_CIF_ISP_MODULE_DPCC (1U << 0)
> /* Black Level Subtraction */
> @@ -53,8 +49,14 @@
> #define RKISP1_CIF_ISP_CTK_COEFF_MAX 0x100
> #define RKISP1_CIF_ISP_CTK_OFFSET_MAX 0x800
>
> -#define RKISP1_CIF_ISP_AE_MEAN_MAX 25
> -#define RKISP1_CIF_ISP_HIST_BIN_N_MAX 16
> +#define RKISP1_CIF_ISP_AE_MEAN_MAX_V10 25
> +#define RKISP1_CIF_ISP_AE_MEAN_MAX_V12 81
> +#define RKISP1_CIF_ISP_AE_MEAN_MAX RKISP1_CIF_ISP_AE_MEAN_MAX_V12
> +
> +#define RKISP1_CIF_ISP_HIST_BIN_N_MAX_V10 16
> +#define RKISP1_CIF_ISP_HIST_BIN_N_MAX_V12 32
> +#define RKISP1_CIF_ISP_HIST_BIN_N_MAX RKISP1_CIF_ISP_HIST_BIN_N_MAX_V12
> +
> #define RKISP1_CIF_ISP_AFM_MAX_WINDOWS 3
> #define RKISP1_CIF_ISP_DEGAMMA_CURVE_SIZE 17
>
> @@ -90,7 +92,9 @@
> * Gamma out
> */
> /* Maximum number of color samples supported */
> -#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES 17
> +#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V10 17
> +#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V12 34
> +#define RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V12
>
> /*
> * Lens shade correction
> @@ -106,8 +110,9 @@
> /*
> * Histogram calculation
> */
> -/* Last 3 values unused. */
> -#define RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 28
> +#define RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V10 25
> +#define RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V12 81
> +#define RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V12
>
> /*
> * Defect Pixel Cluster Correction
> @@ -128,6 +133,21 @@
> #define RKISP1_CIF_ISP_STAT_AFM (1U << 2)
> #define RKISP1_CIF_ISP_STAT_HIST (1U << 3)
>
> +/**
> + * enum rkisp1_cif_isp_version - ISP variants
> + *
> + * @RKISP1_V10: used at least in rk3288 and rk3399
> + * @RKISP1_V11: declared in the original vendor code, but not used
> + * @RKISP1_V12: used at least in rk3326 and px30
> + * @RKISP1_V13: used at least in rk1808
> + */
> +enum rkisp1_cif_isp_version {
> + RKISP1_V10 = 10,
> + RKISP1_V11,
> + RKISP1_V12,
> + RKISP1_V13,
> +};
> +
> enum rkisp1_cif_isp_histogram_mode {
> RKISP1_CIF_ISP_HISTOGRAM_MODE_DISABLE,
> RKISP1_CIF_ISP_HISTOGRAM_MODE_RGB_COMBINED,
> @@ -514,6 +534,15 @@ enum rkisp1_cif_isp_goc_mode {
> *
> * @mode: goc mode (from enum rkisp1_cif_isp_goc_mode)
> * @gamma_y: gamma out curve y-axis for all color components
> + *
> + * The number of entries of @gamma_y depends on the hardware revision
> + * as is reported by the hw_revision field of the struct media_device_info
> + * that is returned by ioctl MEDIA_IOC_DEVICE_INFO.
> + *
> + * Versions <= V11 have RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V10
> + * entries, versions >= V12 have RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V12
> + * entries. RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES is equal to the maximum
> + * of the two.
> */
> struct rkisp1_cif_isp_goc_config {
> __u32 mode;
> @@ -528,6 +557,15 @@ struct rkisp1_cif_isp_goc_config {
> * skipped
> * @meas_window: coordinates of the measure window
> * @hist_weight: weighting factor for sub-windows
> + *
> + * The number of entries of @hist_weight depends on the hardware revision
> + * as is reported by the hw_revision field of the struct media_device_info
> + * that is returned by ioctl MEDIA_IOC_DEVICE_INFO.
> + *
> + * Versions <= V11 have RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V10
> + * entries, versions >= V12 have RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V12
> + * entries. RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE is equal to the maximum
> + * of the two.
> */
> struct rkisp1_cif_isp_hst_config {
> __u32 mode;
> @@ -815,7 +853,15 @@ struct rkisp1_cif_isp_bls_meas_val {
> * @exp_mean: Mean luminance value of block xx
> * @bls_val: BLS measured values
> *
> - * Image is divided into 5x5 blocks.
> + * The number of entries of @exp_mean depends on the hardware revision
> + * as is reported by the hw_revision field of the struct media_device_info
> + * that is returned by ioctl MEDIA_IOC_DEVICE_INFO.
> + *
> + * Versions <= V11 have RKISP1_CIF_ISP_AE_MEAN_MAX_V10 entries,
> + * versions >= V12 have RKISP1_CIF_ISP_AE_MEAN_MAX_V12 entries.
> + * RKISP1_CIF_ISP_AE_MEAN_MAX is equal to the maximum of the two.
> + *
> + * Image is divided into 5x5 blocks on V10 and 9x9 blocks on V12.
> */
> struct rkisp1_cif_isp_ae_stat {
> __u8 exp_mean[RKISP1_CIF_ISP_AE_MEAN_MAX];
> @@ -848,13 +894,29 @@ struct rkisp1_cif_isp_af_stat {
> /**
> * struct rkisp1_cif_isp_hist_stat - statistics histogram data
> *
> - * @hist_bins: measured bin counters
> + * @hist_bins: measured bin counters. Each bin is a 20 bits unsigned fixed point
> + * type. Bits 0-4 are the fractional part and bits 5-19 are the
> + * integer part.
> *
> - * Measurement window divided into 25 sub-windows, set
> - * with ISP_HIST_XXX
> + * The window of the measurements area is divided to 5x5 sub-windows for
> + * V10/V11 and to 9x9 sub-windows for V12. The histogram is then computed for
> + * each sub-window independently and the final result is a weighted average of
> + * the histogram measurements on all sub-windows. The window of the
> + * measurements area and the weight of each sub-window are configurable using
> + * struct @rkisp1_cif_isp_hst_config.
> + *
> + * The histogram contains 16 bins in V10/V11 and 32 bins in V12/V13.
> + *
> + * The number of entries of @hist_bins depends on the hardware revision
> + * as is reported by the hw_revision field of the struct media_device_info
> + * that is returned by ioctl MEDIA_IOC_DEVICE_INFO.
> + *
> + * Versions <= V11 have RKISP1_CIF_ISP_HIST_BIN_N_MAX_V10 entries,
> + * versions >= V12 have RKISP1_CIF_ISP_HIST_BIN_N_MAX_V12 entries.
> + * RKISP1_CIF_ISP_HIST_BIN_N_MAX is equal to the maximum of the two.
> */
> struct rkisp1_cif_isp_hist_stat {
> - __u16 hist_bins[RKISP1_CIF_ISP_HIST_BIN_N_MAX];
> + __u32 hist_bins[RKISP1_CIF_ISP_HIST_BIN_N_MAX];
> };
>
> /**
> diff --git a/include/linux/v4l2-controls.h b/include/linux/v4l2-controls.h
> index 39f4bcb5c564..59a57418947e 100644
> --- a/include/linux/v4l2-controls.h
> +++ b/include/linux/v4l2-controls.h
> @@ -54,7 +54,7 @@
>
> /* Control classes */
> #define V4L2_CTRL_CLASS_USER 0x00980000 /* Old-style 'user' controls */
> -#define V4L2_CTRL_CLASS_MPEG 0x00990000 /* MPEG-compression controls */
> +#define V4L2_CTRL_CLASS_CODEC 0x00990000 /* Stateful codec controls */
> #define V4L2_CTRL_CLASS_CAMERA 0x009a0000 /* Camera class controls */
> #define V4L2_CTRL_CLASS_FM_TX 0x009b0000 /* FM Modulator controls */
> #define V4L2_CTRL_CLASS_FLASH 0x009c0000 /* Camera flash controls */
> @@ -65,6 +65,7 @@
> #define V4L2_CTRL_CLASS_FM_RX 0x00a10000 /* FM Receiver controls */
> #define V4L2_CTRL_CLASS_RF_TUNER 0x00a20000 /* RF tuner controls */
> #define V4L2_CTRL_CLASS_DETECT 0x00a30000 /* Detection controls */
> +#define V4L2_CTRL_CLASS_CODEC_STATELESS 0x00a40000 /* Stateless codecs controls */
>
> /* User-class control IDs */
>
> @@ -198,6 +199,17 @@ enum v4l2_colorfx {
> */
> #define V4L2_CID_USER_ATMEL_ISC_BASE (V4L2_CID_USER_BASE + 0x10c0)
>
> +/*
> + * The base for the CODA driver controls.
> + * We reserve 16 controls for this driver.
> + */
> +#define V4L2_CID_USER_CODA_BASE (V4L2_CID_USER_BASE + 0x10e0)
> +/*
> + * The base for MIPI CCS driver controls.
> + * We reserve 128 controls for this driver.
> + */
> +#define V4L2_CID_USER_CCS_BASE (V4L2_CID_USER_BASE + 0x10f0)
> +
> /* The base for the bcm2835-isp driver controls.
> * We reserve 16 controls for this driver. */
> #define V4L2_CID_USER_BCM2835_ISP_BASE (V4L2_CID_USER_BASE + 0x10e0)
> @@ -206,11 +218,11 @@ enum v4l2_colorfx {
> /* The MPEG controls are applicable to all codec controls
> * and the 'MPEG' part of the define is historical */
>
> -#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900)
> -#define V4L2_CID_MPEG_CLASS (V4L2_CTRL_CLASS_MPEG | 1)
> +#define V4L2_CID_CODEC_BASE (V4L2_CTRL_CLASS_CODEC | 0x900)
> +#define V4L2_CID_CODEC_CLASS (V4L2_CTRL_CLASS_CODEC | 1)
>
> /* MPEG streams, specific to multiplexed streams */
> -#define V4L2_CID_MPEG_STREAM_TYPE (V4L2_CID_MPEG_BASE+0)
> +#define V4L2_CID_MPEG_STREAM_TYPE (V4L2_CID_CODEC_BASE+0)
> enum v4l2_mpeg_stream_type {
> V4L2_MPEG_STREAM_TYPE_MPEG2_PS = 0, /* MPEG-2 program stream */
> V4L2_MPEG_STREAM_TYPE_MPEG2_TS = 1, /* MPEG-2 transport stream */
> @@ -219,26 +231,26 @@ enum v4l2_mpeg_stream_type {
> V4L2_MPEG_STREAM_TYPE_MPEG1_VCD = 4, /* MPEG-1 VCD-compatible stream */
> V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD = 5, /* MPEG-2 SVCD-compatible stream */
> };
> -#define V4L2_CID_MPEG_STREAM_PID_PMT (V4L2_CID_MPEG_BASE+1)
> -#define V4L2_CID_MPEG_STREAM_PID_AUDIO (V4L2_CID_MPEG_BASE+2)
> -#define V4L2_CID_MPEG_STREAM_PID_VIDEO (V4L2_CID_MPEG_BASE+3)
> -#define V4L2_CID_MPEG_STREAM_PID_PCR (V4L2_CID_MPEG_BASE+4)
> -#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO (V4L2_CID_MPEG_BASE+5)
> -#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO (V4L2_CID_MPEG_BASE+6)
> -#define V4L2_CID_MPEG_STREAM_VBI_FMT (V4L2_CID_MPEG_BASE+7)
> +#define V4L2_CID_MPEG_STREAM_PID_PMT (V4L2_CID_CODEC_BASE+1)
> +#define V4L2_CID_MPEG_STREAM_PID_AUDIO (V4L2_CID_CODEC_BASE+2)
> +#define V4L2_CID_MPEG_STREAM_PID_VIDEO (V4L2_CID_CODEC_BASE+3)
> +#define V4L2_CID_MPEG_STREAM_PID_PCR (V4L2_CID_CODEC_BASE+4)
> +#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO (V4L2_CID_CODEC_BASE+5)
> +#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO (V4L2_CID_CODEC_BASE+6)
> +#define V4L2_CID_MPEG_STREAM_VBI_FMT (V4L2_CID_CODEC_BASE+7)
> enum v4l2_mpeg_stream_vbi_fmt {
> V4L2_MPEG_STREAM_VBI_FMT_NONE = 0, /* No VBI in the MPEG stream */
> V4L2_MPEG_STREAM_VBI_FMT_IVTV = 1, /* VBI in private packets, IVTV format */
> };
>
> /* MPEG audio controls specific to multiplexed streams */
> -#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ (V4L2_CID_MPEG_BASE+100)
> +#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ (V4L2_CID_CODEC_BASE+100)
> enum v4l2_mpeg_audio_sampling_freq {
> V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100 = 0,
> V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000 = 1,
> V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000 = 2,
> };
> -#define V4L2_CID_MPEG_AUDIO_ENCODING (V4L2_CID_MPEG_BASE+101)
> +#define V4L2_CID_MPEG_AUDIO_ENCODING (V4L2_CID_CODEC_BASE+101)
> enum v4l2_mpeg_audio_encoding {
> V4L2_MPEG_AUDIO_ENCODING_LAYER_1 = 0,
> V4L2_MPEG_AUDIO_ENCODING_LAYER_2 = 1,
> @@ -246,7 +258,7 @@ enum v4l2_mpeg_audio_encoding {
> V4L2_MPEG_AUDIO_ENCODING_AAC = 3,
> V4L2_MPEG_AUDIO_ENCODING_AC3 = 4,
> };
> -#define V4L2_CID_MPEG_AUDIO_L1_BITRATE (V4L2_CID_MPEG_BASE+102)
> +#define V4L2_CID_MPEG_AUDIO_L1_BITRATE (V4L2_CID_CODEC_BASE+102)
> enum v4l2_mpeg_audio_l1_bitrate {
> V4L2_MPEG_AUDIO_L1_BITRATE_32K = 0,
> V4L2_MPEG_AUDIO_L1_BITRATE_64K = 1,
> @@ -263,7 +275,7 @@ enum v4l2_mpeg_audio_l1_bitrate {
> V4L2_MPEG_AUDIO_L1_BITRATE_416K = 12,
> V4L2_MPEG_AUDIO_L1_BITRATE_448K = 13,
> };
> -#define V4L2_CID_MPEG_AUDIO_L2_BITRATE (V4L2_CID_MPEG_BASE+103)
> +#define V4L2_CID_MPEG_AUDIO_L2_BITRATE (V4L2_CID_CODEC_BASE+103)
> enum v4l2_mpeg_audio_l2_bitrate {
> V4L2_MPEG_AUDIO_L2_BITRATE_32K = 0,
> V4L2_MPEG_AUDIO_L2_BITRATE_48K = 1,
> @@ -280,7 +292,7 @@ enum v4l2_mpeg_audio_l2_bitrate {
> V4L2_MPEG_AUDIO_L2_BITRATE_320K = 12,
> V4L2_MPEG_AUDIO_L2_BITRATE_384K = 13,
> };
> -#define V4L2_CID_MPEG_AUDIO_L3_BITRATE (V4L2_CID_MPEG_BASE+104)
> +#define V4L2_CID_MPEG_AUDIO_L3_BITRATE (V4L2_CID_CODEC_BASE+104)
> enum v4l2_mpeg_audio_l3_bitrate {
> V4L2_MPEG_AUDIO_L3_BITRATE_32K = 0,
> V4L2_MPEG_AUDIO_L3_BITRATE_40K = 1,
> @@ -297,34 +309,34 @@ enum v4l2_mpeg_audio_l3_bitrate {
> V4L2_MPEG_AUDIO_L3_BITRATE_256K = 12,
> V4L2_MPEG_AUDIO_L3_BITRATE_320K = 13,
> };
> -#define V4L2_CID_MPEG_AUDIO_MODE (V4L2_CID_MPEG_BASE+105)
> +#define V4L2_CID_MPEG_AUDIO_MODE (V4L2_CID_CODEC_BASE+105)
> enum v4l2_mpeg_audio_mode {
> V4L2_MPEG_AUDIO_MODE_STEREO = 0,
> V4L2_MPEG_AUDIO_MODE_JOINT_STEREO = 1,
> V4L2_MPEG_AUDIO_MODE_DUAL = 2,
> V4L2_MPEG_AUDIO_MODE_MONO = 3,
> };
> -#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION (V4L2_CID_MPEG_BASE+106)
> +#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION (V4L2_CID_CODEC_BASE+106)
> enum v4l2_mpeg_audio_mode_extension {
> V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4 = 0,
> V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8 = 1,
> V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12 = 2,
> V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16 = 3,
> };
> -#define V4L2_CID_MPEG_AUDIO_EMPHASIS (V4L2_CID_MPEG_BASE+107)
> +#define V4L2_CID_MPEG_AUDIO_EMPHASIS (V4L2_CID_CODEC_BASE+107)
> enum v4l2_mpeg_audio_emphasis {
> V4L2_MPEG_AUDIO_EMPHASIS_NONE = 0,
> V4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS = 1,
> V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17 = 2,
> };
> -#define V4L2_CID_MPEG_AUDIO_CRC (V4L2_CID_MPEG_BASE+108)
> +#define V4L2_CID_MPEG_AUDIO_CRC (V4L2_CID_CODEC_BASE+108)
> enum v4l2_mpeg_audio_crc {
> V4L2_MPEG_AUDIO_CRC_NONE = 0,
> V4L2_MPEG_AUDIO_CRC_CRC16 = 1,
> };
> -#define V4L2_CID_MPEG_AUDIO_MUTE (V4L2_CID_MPEG_BASE+109)
> -#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE (V4L2_CID_MPEG_BASE+110)
> -#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE (V4L2_CID_MPEG_BASE+111)
> +#define V4L2_CID_MPEG_AUDIO_MUTE (V4L2_CID_CODEC_BASE+109)
> +#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE (V4L2_CID_CODEC_BASE+110)
> +#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE (V4L2_CID_CODEC_BASE+111)
> enum v4l2_mpeg_audio_ac3_bitrate {
> V4L2_MPEG_AUDIO_AC3_BITRATE_32K = 0,
> V4L2_MPEG_AUDIO_AC3_BITRATE_40K = 1,
> @@ -346,7 +358,7 @@ enum v4l2_mpeg_audio_ac3_bitrate {
> V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17,
> V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18,
> };
> -#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK (V4L2_CID_MPEG_BASE+112)
> +#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK (V4L2_CID_CODEC_BASE+112)
> enum v4l2_mpeg_audio_dec_playback {
> V4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO = 0,
> V4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO = 1,
> @@ -355,51 +367,52 @@ enum v4l2_mpeg_audio_dec_playback {
> V4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO = 4,
> V4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO = 5,
> };
> -#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_MPEG_BASE+113)
> +#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_CODEC_BASE+113)
>
> /* MPEG video controls specific to multiplexed streams */
> -#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE+200)
> +#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_CODEC_BASE+200)
> enum v4l2_mpeg_video_encoding {
> V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0,
> V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1,
> V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2,
> };
> -#define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_MPEG_BASE+201)
> +#define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_CODEC_BASE+201)
> enum v4l2_mpeg_video_aspect {
> V4L2_MPEG_VIDEO_ASPECT_1x1 = 0,
> V4L2_MPEG_VIDEO_ASPECT_4x3 = 1,
> V4L2_MPEG_VIDEO_ASPECT_16x9 = 2,
> V4L2_MPEG_VIDEO_ASPECT_221x100 = 3,
> };
> -#define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_MPEG_BASE+202)
> -#define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_MPEG_BASE+203)
> -#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_MPEG_BASE+204)
> -#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_MPEG_BASE+205)
> -#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_MPEG_BASE+206)
> +#define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_CODEC_BASE+202)
> +#define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_CODEC_BASE+203)
> +#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_CODEC_BASE+204)
> +#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_CODEC_BASE+205)
> +#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_CODEC_BASE+206)
> enum v4l2_mpeg_video_bitrate_mode {
> V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0,
> V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1,
> + V4L2_MPEG_VIDEO_BITRATE_MODE_CQ = 2,
> };
> -#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_MPEG_BASE+207)
> -#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_MPEG_BASE+208)
> -#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_MPEG_BASE+209)
> -#define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_MPEG_BASE+210)
> -#define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_MPEG_BASE+211)
> -#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (V4L2_CID_MPEG_BASE+212)
> -#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER (V4L2_CID_MPEG_BASE+213)
> -#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (V4L2_CID_MPEG_BASE+214)
> -#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE (V4L2_CID_MPEG_BASE+215)
> -#define V4L2_CID_MPEG_VIDEO_HEADER_MODE (V4L2_CID_MPEG_BASE+216)
> +#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_CODEC_BASE+207)
> +#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_CODEC_BASE+208)
> +#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_CODEC_BASE+209)
> +#define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_CODEC_BASE+210)
> +#define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_CODEC_BASE+211)
> +#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (V4L2_CID_CODEC_BASE+212)
> +#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER (V4L2_CID_CODEC_BASE+213)
> +#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (V4L2_CID_CODEC_BASE+214)
> +#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE (V4L2_CID_CODEC_BASE+215)
> +#define V4L2_CID_MPEG_VIDEO_HEADER_MODE (V4L2_CID_CODEC_BASE+216)
> enum v4l2_mpeg_video_header_mode {
> V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0,
> V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1,
>
> };
> -#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_MPEG_BASE+217)
> -#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_MPEG_BASE+218)
> -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES (V4L2_CID_MPEG_BASE+219)
> -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB (V4L2_CID_MPEG_BASE+220)
> -#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE (V4L2_CID_MPEG_BASE+221)
> +#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_CODEC_BASE+217)
> +#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_CODEC_BASE+218)
> +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES (V4L2_CID_CODEC_BASE+219)
> +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB (V4L2_CID_CODEC_BASE+220)
> +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE (V4L2_CID_CODEC_BASE+221)
> enum v4l2_mpeg_video_multi_slice_mode {
> V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE = 0,
> V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB = 1,
> @@ -408,24 +421,25 @@ enum v4l2_mpeg_video_multi_slice_mode {
> V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB = 1,
> V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2,
> };
> -#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE+222)
> -#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_MPEG_BASE+223)
> -#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE+224)
> -#define V4L2_CID_MPEG_VIDEO_VBV_DELAY (V4L2_CID_MPEG_BASE+225)
> -#define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER (V4L2_CID_MPEG_BASE+226)
> -#define V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE (V4L2_CID_MPEG_BASE+227)
> -#define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE (V4L2_CID_MPEG_BASE+228)
> -#define V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME (V4L2_CID_MPEG_BASE+229)
> +#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_CODEC_BASE+222)
> +#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_CODEC_BASE+223)
> +#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_CODEC_BASE+224)
> +#define V4L2_CID_MPEG_VIDEO_VBV_DELAY (V4L2_CID_CODEC_BASE+225)
> +#define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER (V4L2_CID_CODEC_BASE+226)
> +#define V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE (V4L2_CID_CODEC_BASE+227)
> +#define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE (V4L2_CID_CODEC_BASE+228)
> +#define V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME (V4L2_CID_CODEC_BASE+229)
> +#define V4L2_CID_MPEG_VIDEO_BASELAYER_PRIORITY_ID (V4L2_CID_CODEC_BASE+230)
>
> /* CIDs for the MPEG-2 Part 2 (H.262) codec */
> -#define V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL (V4L2_CID_MPEG_BASE+270)
> +#define V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL (V4L2_CID_CODEC_BASE+270)
> enum v4l2_mpeg_video_mpeg2_level {
> V4L2_MPEG_VIDEO_MPEG2_LEVEL_LOW = 0,
> V4L2_MPEG_VIDEO_MPEG2_LEVEL_MAIN = 1,
> V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH_1440 = 2,
> V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH = 3,
> };
> -#define V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE (V4L2_CID_MPEG_BASE+271)
> +#define V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE (V4L2_CID_CODEC_BASE+271)
> enum v4l2_mpeg_video_mpeg2_profile {
> V4L2_MPEG_VIDEO_MPEG2_PROFILE_SIMPLE = 0,
> V4L2_MPEG_VIDEO_MPEG2_PROFILE_MAIN = 1,
> @@ -436,28 +450,28 @@ enum v4l2_mpeg_video_mpeg2_profile {
> };
>
> /* CIDs for the FWHT codec as used by the vicodec driver. */
> -#define V4L2_CID_FWHT_I_FRAME_QP (V4L2_CID_MPEG_BASE + 290)
> -#define V4L2_CID_FWHT_P_FRAME_QP (V4L2_CID_MPEG_BASE + 291)
> +#define V4L2_CID_FWHT_I_FRAME_QP (V4L2_CID_CODEC_BASE + 290)
> +#define V4L2_CID_FWHT_P_FRAME_QP (V4L2_CID_CODEC_BASE + 291)
>
> -#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300)
> -#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301)
> -#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_MPEG_BASE+302)
> -#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP (V4L2_CID_MPEG_BASE+303)
> -#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP (V4L2_CID_MPEG_BASE+304)
> -#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_MPEG_BASE+350)
> -#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP (V4L2_CID_MPEG_BASE+351)
> -#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP (V4L2_CID_MPEG_BASE+352)
> -#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP (V4L2_CID_MPEG_BASE+353)
> -#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_MPEG_BASE+354)
> -#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (V4L2_CID_MPEG_BASE+355)
> -#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE (V4L2_CID_MPEG_BASE+356)
> -#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE (V4L2_CID_MPEG_BASE+357)
> +#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_CODEC_BASE+300)
> +#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_CODEC_BASE+301)
> +#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_CODEC_BASE+302)
> +#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP (V4L2_CID_CODEC_BASE+303)
> +#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP (V4L2_CID_CODEC_BASE+304)
> +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_CODEC_BASE+350)
> +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP (V4L2_CID_CODEC_BASE+351)
> +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP (V4L2_CID_CODEC_BASE+352)
> +#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP (V4L2_CID_CODEC_BASE+353)
> +#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_CODEC_BASE+354)
> +#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (V4L2_CID_CODEC_BASE+355)
> +#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE (V4L2_CID_CODEC_BASE+356)
> +#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE (V4L2_CID_CODEC_BASE+357)
> enum v4l2_mpeg_video_h264_entropy_mode {
> V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC = 0,
> V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC = 1,
> };
> -#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_MPEG_BASE+358)
> -#define V4L2_CID_MPEG_VIDEO_H264_LEVEL (V4L2_CID_MPEG_BASE+359)
> +#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_CODEC_BASE+358)
> +#define V4L2_CID_MPEG_VIDEO_H264_LEVEL (V4L2_CID_CODEC_BASE+359)
> enum v4l2_mpeg_video_h264_level {
> V4L2_MPEG_VIDEO_H264_LEVEL_1_0 = 0,
> V4L2_MPEG_VIDEO_H264_LEVEL_1B = 1,
> @@ -475,16 +489,20 @@ enum v4l2_mpeg_video_h264_level {
> V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13,
> V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14,
> V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15,
> + V4L2_MPEG_VIDEO_H264_LEVEL_5_2 = 16,
> + V4L2_MPEG_VIDEO_H264_LEVEL_6_0 = 17,
> + V4L2_MPEG_VIDEO_H264_LEVEL_6_1 = 18,
> + V4L2_MPEG_VIDEO_H264_LEVEL_6_2 = 19,
> };
> -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE+360)
> -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_MPEG_BASE+361)
> -#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE (V4L2_CID_MPEG_BASE+362)
> +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_CODEC_BASE+360)
> +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_CODEC_BASE+361)
> +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE (V4L2_CID_CODEC_BASE+362)
> enum v4l2_mpeg_video_h264_loop_filter_mode {
> V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED = 0,
> V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED = 1,
> V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY = 2,
> };
> -#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_MPEG_BASE+363)
> +#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_CODEC_BASE+363)
> enum v4l2_mpeg_video_h264_profile {
> V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE = 0,
> V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE = 1,
> @@ -503,11 +521,12 @@ enum v4l2_mpeg_video_h264_profile {
> V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14,
> V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15,
> V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16,
> + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH = 17,
> };
> -#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+364)
> -#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE+365)
> -#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (V4L2_CID_MPEG_BASE+366)
> -#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC (V4L2_CID_MPEG_BASE+367)
> +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_CODEC_BASE+364)
> +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_CODEC_BASE+365)
> +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (V4L2_CID_CODEC_BASE+366)
> +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC (V4L2_CID_CODEC_BASE+367)
> enum v4l2_mpeg_video_h264_vui_sar_idc {
> V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED = 0,
> V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 = 1,
> @@ -528,9 +547,9 @@ enum v4l2_mpeg_video_h264_vui_sar_idc {
> V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 = 16,
> V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED = 17,
> };
> -#define V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING (V4L2_CID_MPEG_BASE+368)
> -#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0 (V4L2_CID_MPEG_BASE+369)
> -#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE (V4L2_CID_MPEG_BASE+370)
> +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING (V4L2_CID_CODEC_BASE+368)
> +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0 (V4L2_CID_CODEC_BASE+369)
> +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE (V4L2_CID_CODEC_BASE+370)
> enum v4l2_mpeg_video_h264_sei_fp_arrangement_type {
> V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_CHECKERBOARD = 0,
> V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_COLUMN = 1,
> @@ -539,8 +558,8 @@ enum v4l2_mpeg_video_h264_sei_fp_arrangement_type {
> V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TOP_BOTTOM = 4,
> V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TEMPORAL = 5,
> };
> -#define V4L2_CID_MPEG_VIDEO_H264_FMO (V4L2_CID_MPEG_BASE+371)
> -#define V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE (V4L2_CID_MPEG_BASE+372)
> +#define V4L2_CID_MPEG_VIDEO_H264_FMO (V4L2_CID_CODEC_BASE+371)
> +#define V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE (V4L2_CID_CODEC_BASE+372)
> enum v4l2_mpeg_video_h264_fmo_map_type {
> V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES = 0,
> V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES = 1,
> @@ -550,36 +569,45 @@ enum v4l2_mpeg_video_h264_fmo_map_type {
> V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN = 5,
> V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_EXPLICIT = 6,
> };
> -#define V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP (V4L2_CID_MPEG_BASE+373)
> -#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION (V4L2_CID_MPEG_BASE+374)
> +#define V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP (V4L2_CID_CODEC_BASE+373)
> +#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION (V4L2_CID_CODEC_BASE+374)
> enum v4l2_mpeg_video_h264_fmo_change_dir {
> V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT = 0,
> V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_LEFT = 1,
> };
> -#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE (V4L2_CID_MPEG_BASE+375)
> -#define V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH (V4L2_CID_MPEG_BASE+376)
> -#define V4L2_CID_MPEG_VIDEO_H264_ASO (V4L2_CID_MPEG_BASE+377)
> -#define V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER (V4L2_CID_MPEG_BASE+378)
> -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING (V4L2_CID_MPEG_BASE+379)
> -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE (V4L2_CID_MPEG_BASE+380)
> +#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE (V4L2_CID_CODEC_BASE+375)
> +#define V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH (V4L2_CID_CODEC_BASE+376)
> +#define V4L2_CID_MPEG_VIDEO_H264_ASO (V4L2_CID_CODEC_BASE+377)
> +#define V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER (V4L2_CID_CODEC_BASE+378)
> +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING (V4L2_CID_CODEC_BASE+379)
> +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE (V4L2_CID_CODEC_BASE+380)
> enum v4l2_mpeg_video_h264_hierarchical_coding_type {
> V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B = 0,
> V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P = 1,
> };
> -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER (V4L2_CID_MPEG_BASE+381)
> -#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_MPEG_BASE+382)
> -#define V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION (V4L2_CID_MPEG_BASE+383)
> -#define V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET (V4L2_CID_MPEG_BASE+384)
> -#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP (V4L2_CID_MPEG_BASE+385)
> -#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP (V4L2_CID_MPEG_BASE+386)
> -#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP (V4L2_CID_MPEG_BASE+387)
> -#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP (V4L2_CID_MPEG_BASE+388)
> -#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400)
> -#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401)
> -#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402)
> -#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_MPEG_BASE+403)
> -#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_MPEG_BASE+404)
> -#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_MPEG_BASE+405)
> +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER (V4L2_CID_CODEC_BASE+381)
> +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_CODEC_BASE+382)
> +#define V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION (V4L2_CID_CODEC_BASE+383)
> +#define V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET (V4L2_CID_CODEC_BASE+384)
> +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP (V4L2_CID_CODEC_BASE+385)
> +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP (V4L2_CID_CODEC_BASE+386)
> +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP (V4L2_CID_CODEC_BASE+387)
> +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP (V4L2_CID_CODEC_BASE+388)
> +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP (V4L2_CID_CODEC_BASE+389)
> +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP (V4L2_CID_CODEC_BASE+390)
> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L0_BR (V4L2_CID_CODEC_BASE+391)
> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L1_BR (V4L2_CID_CODEC_BASE+392)
> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L2_BR (V4L2_CID_CODEC_BASE+393)
> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L3_BR (V4L2_CID_CODEC_BASE+394)
> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L4_BR (V4L2_CID_CODEC_BASE+395)
> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L5_BR (V4L2_CID_CODEC_BASE+396)
> +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L6_BR (V4L2_CID_CODEC_BASE+397)
> +#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_CODEC_BASE+400)
> +#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_CODEC_BASE+401)
> +#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_CODEC_BASE+402)
> +#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_CODEC_BASE+403)
> +#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_CODEC_BASE+404)
> +#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_CODEC_BASE+405)
> enum v4l2_mpeg_video_mpeg4_level {
> V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 = 0,
> V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1,
> @@ -590,7 +618,7 @@ enum v4l2_mpeg_video_mpeg4_level {
> V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 = 6,
> V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 = 7,
> };
> -#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_MPEG_BASE+406)
> +#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_CODEC_BASE+406)
> enum v4l2_mpeg_video_mpeg4_profile {
> V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE = 0,
> V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE = 1,
> @@ -598,40 +626,40 @@ enum v4l2_mpeg_video_mpeg4_profile {
> V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE = 3,
> V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY = 4,
> };
> -#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_MPEG_BASE+407)
> +#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_CODEC_BASE+407)
>
> /* Control IDs for VP8 streams
> * Although VP8 is not part of MPEG we add these controls to the MPEG class
> * as that class is already handling other video compression standards
> */
> -#define V4L2_CID_MPEG_VIDEO_VPX_NUM_PARTITIONS (V4L2_CID_MPEG_BASE+500)
> +#define V4L2_CID_MPEG_VIDEO_VPX_NUM_PARTITIONS (V4L2_CID_CODEC_BASE+500)
> enum v4l2_vp8_num_partitions {
> V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION = 0,
> V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS = 1,
> V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS = 2,
> V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS = 3,
> };
> -#define V4L2_CID_MPEG_VIDEO_VPX_IMD_DISABLE_4X4 (V4L2_CID_MPEG_BASE+501)
> -#define V4L2_CID_MPEG_VIDEO_VPX_NUM_REF_FRAMES (V4L2_CID_MPEG_BASE+502)
> +#define V4L2_CID_MPEG_VIDEO_VPX_IMD_DISABLE_4X4 (V4L2_CID_CODEC_BASE+501)
> +#define V4L2_CID_MPEG_VIDEO_VPX_NUM_REF_FRAMES (V4L2_CID_CODEC_BASE+502)
> enum v4l2_vp8_num_ref_frames {
> V4L2_CID_MPEG_VIDEO_VPX_1_REF_FRAME = 0,
> V4L2_CID_MPEG_VIDEO_VPX_2_REF_FRAME = 1,
> V4L2_CID_MPEG_VIDEO_VPX_3_REF_FRAME = 2,
> };
> -#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_LEVEL (V4L2_CID_MPEG_BASE+503)
> -#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_SHARPNESS (V4L2_CID_MPEG_BASE+504)
> -#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_REF_PERIOD (V4L2_CID_MPEG_BASE+505)
> -#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_SEL (V4L2_CID_MPEG_BASE+506)
> +#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_LEVEL (V4L2_CID_CODEC_BASE+503)
> +#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_SHARPNESS (V4L2_CID_CODEC_BASE+504)
> +#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_REF_PERIOD (V4L2_CID_CODEC_BASE+505)
> +#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_SEL (V4L2_CID_CODEC_BASE+506)
> enum v4l2_vp8_golden_frame_sel {
> V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_PREV = 0,
> V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_REF_PERIOD = 1,
> };
> -#define V4L2_CID_MPEG_VIDEO_VPX_MIN_QP (V4L2_CID_MPEG_BASE+507)
> -#define V4L2_CID_MPEG_VIDEO_VPX_MAX_QP (V4L2_CID_MPEG_BASE+508)
> -#define V4L2_CID_MPEG_VIDEO_VPX_I_FRAME_QP (V4L2_CID_MPEG_BASE+509)
> -#define V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP (V4L2_CID_MPEG_BASE+510)
> +#define V4L2_CID_MPEG_VIDEO_VPX_MIN_QP (V4L2_CID_CODEC_BASE+507)
> +#define V4L2_CID_MPEG_VIDEO_VPX_MAX_QP (V4L2_CID_CODEC_BASE+508)
> +#define V4L2_CID_MPEG_VIDEO_VPX_I_FRAME_QP (V4L2_CID_CODEC_BASE+509)
> +#define V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP (V4L2_CID_CODEC_BASE+510)
>
> -#define V4L2_CID_MPEG_VIDEO_VP8_PROFILE (V4L2_CID_MPEG_BASE+511)
> +#define V4L2_CID_MPEG_VIDEO_VP8_PROFILE (V4L2_CID_CODEC_BASE+511)
> enum v4l2_mpeg_video_vp8_profile {
> V4L2_MPEG_VIDEO_VP8_PROFILE_0 = 0,
> V4L2_MPEG_VIDEO_VP8_PROFILE_1 = 1,
> @@ -640,42 +668,59 @@ enum v4l2_mpeg_video_vp8_profile {
> };
> /* Deprecated alias for compatibility reasons. */
> #define V4L2_CID_MPEG_VIDEO_VPX_PROFILE V4L2_CID_MPEG_VIDEO_VP8_PROFILE
> -#define V4L2_CID_MPEG_VIDEO_VP9_PROFILE (V4L2_CID_MPEG_BASE+512)
> +#define V4L2_CID_MPEG_VIDEO_VP9_PROFILE (V4L2_CID_CODEC_BASE+512)
> enum v4l2_mpeg_video_vp9_profile {
> V4L2_MPEG_VIDEO_VP9_PROFILE_0 = 0,
> V4L2_MPEG_VIDEO_VP9_PROFILE_1 = 1,
> V4L2_MPEG_VIDEO_VP9_PROFILE_2 = 2,
> V4L2_MPEG_VIDEO_VP9_PROFILE_3 = 3,
> };
> +#define V4L2_CID_MPEG_VIDEO_VP9_LEVEL (V4L2_CID_CODEC_BASE+513)
> +enum v4l2_mpeg_video_vp9_level {
> + V4L2_MPEG_VIDEO_VP9_LEVEL_1_0 = 0,
> + V4L2_MPEG_VIDEO_VP9_LEVEL_1_1 = 1,
> + V4L2_MPEG_VIDEO_VP9_LEVEL_2_0 = 2,
> + V4L2_MPEG_VIDEO_VP9_LEVEL_2_1 = 3,
> + V4L2_MPEG_VIDEO_VP9_LEVEL_3_0 = 4,
> + V4L2_MPEG_VIDEO_VP9_LEVEL_3_1 = 5,
> + V4L2_MPEG_VIDEO_VP9_LEVEL_4_0 = 6,
> + V4L2_MPEG_VIDEO_VP9_LEVEL_4_1 = 7,
> + V4L2_MPEG_VIDEO_VP9_LEVEL_5_0 = 8,
> + V4L2_MPEG_VIDEO_VP9_LEVEL_5_1 = 9,
> + V4L2_MPEG_VIDEO_VP9_LEVEL_5_2 = 10,
> + V4L2_MPEG_VIDEO_VP9_LEVEL_6_0 = 11,
> + V4L2_MPEG_VIDEO_VP9_LEVEL_6_1 = 12,
> + V4L2_MPEG_VIDEO_VP9_LEVEL_6_2 = 13,
> +};
>
> /* CIDs for HEVC encoding. */
>
> -#define V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP (V4L2_CID_MPEG_BASE + 600)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP (V4L2_CID_MPEG_BASE + 601)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP (V4L2_CID_MPEG_BASE + 602)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP (V4L2_CID_MPEG_BASE + 603)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP (V4L2_CID_MPEG_BASE + 604)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_QP (V4L2_CID_MPEG_BASE + 605)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE (V4L2_CID_MPEG_BASE + 606)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP (V4L2_CID_CODEC_BASE + 600)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP (V4L2_CID_CODEC_BASE + 601)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP (V4L2_CID_CODEC_BASE + 602)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP (V4L2_CID_CODEC_BASE + 603)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP (V4L2_CID_CODEC_BASE + 604)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_QP (V4L2_CID_CODEC_BASE + 605)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE (V4L2_CID_CODEC_BASE + 606)
> enum v4l2_mpeg_video_hevc_hier_coding_type {
> V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B = 0,
> V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P = 1,
> };
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER (V4L2_CID_MPEG_BASE + 607)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_QP (V4L2_CID_MPEG_BASE + 608)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_QP (V4L2_CID_MPEG_BASE + 609)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_QP (V4L2_CID_MPEG_BASE + 610)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_QP (V4L2_CID_MPEG_BASE + 611)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_QP (V4L2_CID_MPEG_BASE + 612)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_QP (V4L2_CID_MPEG_BASE + 613)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_QP (V4L2_CID_MPEG_BASE + 614)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_PROFILE (V4L2_CID_MPEG_BASE + 615)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER (V4L2_CID_CODEC_BASE + 607)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_QP (V4L2_CID_CODEC_BASE + 608)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_QP (V4L2_CID_CODEC_BASE + 609)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_QP (V4L2_CID_CODEC_BASE + 610)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_QP (V4L2_CID_CODEC_BASE + 611)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_QP (V4L2_CID_CODEC_BASE + 612)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_QP (V4L2_CID_CODEC_BASE + 613)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_QP (V4L2_CID_CODEC_BASE + 614)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_PROFILE (V4L2_CID_CODEC_BASE + 615)
> enum v4l2_mpeg_video_hevc_profile {
> V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN = 0,
> V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE = 1,
> V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10 = 2,
> };
> -#define V4L2_CID_MPEG_VIDEO_HEVC_LEVEL (V4L2_CID_MPEG_BASE + 616)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_LEVEL (V4L2_CID_CODEC_BASE + 616)
> enum v4l2_mpeg_video_hevc_level {
> V4L2_MPEG_VIDEO_HEVC_LEVEL_1 = 0,
> V4L2_MPEG_VIDEO_HEVC_LEVEL_2 = 1,
> @@ -691,64 +736,78 @@ enum v4l2_mpeg_video_hevc_level {
> V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1 = 11,
> V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2 = 12,
> };
> -#define V4L2_CID_MPEG_VIDEO_HEVC_FRAME_RATE_RESOLUTION (V4L2_CID_MPEG_BASE + 617)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_TIER (V4L2_CID_MPEG_BASE + 618)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_FRAME_RATE_RESOLUTION (V4L2_CID_CODEC_BASE + 617)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_TIER (V4L2_CID_CODEC_BASE + 618)
> enum v4l2_mpeg_video_hevc_tier {
> V4L2_MPEG_VIDEO_HEVC_TIER_MAIN = 0,
> V4L2_MPEG_VIDEO_HEVC_TIER_HIGH = 1,
> };
> -#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH (V4L2_CID_MPEG_BASE + 619)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE (V4L2_CID_MPEG_BASE + 620)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH (V4L2_CID_CODEC_BASE + 619)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE (V4L2_CID_CODEC_BASE + 620)
> enum v4l2_cid_mpeg_video_hevc_loop_filter_mode {
> V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED = 0,
> V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED = 1,
> V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY = 2,
> };
> -#define V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2 (V4L2_CID_MPEG_BASE + 621)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2 (V4L2_CID_MPEG_BASE + 622)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE (V4L2_CID_MPEG_BASE + 623)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2 (V4L2_CID_CODEC_BASE + 621)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2 (V4L2_CID_CODEC_BASE + 622)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE (V4L2_CID_CODEC_BASE + 623)
> enum v4l2_cid_mpeg_video_hevc_refresh_type {
> V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE = 0,
> V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA = 1,
> V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR = 2,
> };
> -#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD (V4L2_CID_MPEG_BASE + 624)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU (V4L2_CID_MPEG_BASE + 625)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED (V4L2_CID_MPEG_BASE + 626)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT (V4L2_CID_MPEG_BASE + 627)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB (V4L2_CID_MPEG_BASE + 628)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID (V4L2_CID_MPEG_BASE + 629)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING (V4L2_CID_MPEG_BASE + 630)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1 (V4L2_CID_MPEG_BASE + 631)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_INTRA_PU_SPLIT (V4L2_CID_MPEG_BASE + 632)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION (V4L2_CID_MPEG_BASE + 633)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE (V4L2_CID_MPEG_BASE + 634)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD (V4L2_CID_MPEG_BASE + 635)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD (V4L2_CID_CODEC_BASE + 624)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU (V4L2_CID_CODEC_BASE + 625)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED (V4L2_CID_CODEC_BASE + 626)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT (V4L2_CID_CODEC_BASE + 627)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB (V4L2_CID_CODEC_BASE + 628)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID (V4L2_CID_CODEC_BASE + 629)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING (V4L2_CID_CODEC_BASE + 630)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1 (V4L2_CID_CODEC_BASE + 631)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_INTRA_PU_SPLIT (V4L2_CID_CODEC_BASE + 632)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION (V4L2_CID_CODEC_BASE + 633)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE (V4L2_CID_CODEC_BASE + 634)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD (V4L2_CID_CODEC_BASE + 635)
> enum v4l2_cid_mpeg_video_hevc_size_of_length_field {
> V4L2_MPEG_VIDEO_HEVC_SIZE_0 = 0,
> V4L2_MPEG_VIDEO_HEVC_SIZE_1 = 1,
> V4L2_MPEG_VIDEO_HEVC_SIZE_2 = 2,
> V4L2_MPEG_VIDEO_HEVC_SIZE_4 = 3,
> };
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_BR (V4L2_CID_MPEG_BASE + 636)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_BR (V4L2_CID_MPEG_BASE + 637)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_BR (V4L2_CID_MPEG_BASE + 638)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_BR (V4L2_CID_MPEG_BASE + 639)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_BR (V4L2_CID_MPEG_BASE + 640)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_BR (V4L2_CID_MPEG_BASE + 641)
> -#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_BR (V4L2_CID_MPEG_BASE + 642)
> -#define V4L2_CID_MPEG_VIDEO_REF_NUMBER_FOR_PFRAMES (V4L2_CID_MPEG_BASE + 643)
> -#define V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR (V4L2_CID_MPEG_BASE + 644)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_BR (V4L2_CID_CODEC_BASE + 636)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_BR (V4L2_CID_CODEC_BASE + 637)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_BR (V4L2_CID_CODEC_BASE + 638)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_BR (V4L2_CID_CODEC_BASE + 639)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_BR (V4L2_CID_CODEC_BASE + 640)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_BR (V4L2_CID_CODEC_BASE + 641)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_BR (V4L2_CID_CODEC_BASE + 642)
> +#define V4L2_CID_MPEG_VIDEO_REF_NUMBER_FOR_PFRAMES (V4L2_CID_CODEC_BASE + 643)
> +#define V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR (V4L2_CID_CODEC_BASE + 644)
> +#define V4L2_CID_MPEG_VIDEO_CONSTANT_QUALITY (V4L2_CID_CODEC_BASE + 645)
> +#define V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE (V4L2_CID_CODEC_BASE + 646)
> +enum v4l2_mpeg_video_frame_skip_mode {
> + V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED = 0,
> + V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT = 1,
> + V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT = 2,
> +};
> +
> +#define V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP (V4L2_CID_CODEC_BASE + 647)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP (V4L2_CID_CODEC_BASE + 648)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP (V4L2_CID_CODEC_BASE + 649)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP (V4L2_CID_CODEC_BASE + 650)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP (V4L2_CID_CODEC_BASE + 651)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP (V4L2_CID_CODEC_BASE + 652)
>
> /* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */
> -#define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000)
> -#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+0)
> +#define V4L2_CID_CODEC_CX2341X_BASE (V4L2_CTRL_CLASS_CODEC | 0x1000)
> +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_CODEC_CX2341X_BASE+0)
> enum v4l2_mpeg_cx2341x_video_spatial_filter_mode {
> V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0,
> V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO = 1,
> };
> -#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+1)
> -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+2)
> +#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER (V4L2_CID_CODEC_CX2341X_BASE+1)
> +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_CODEC_CX2341X_BASE+2)
> enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type {
> V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF = 0,
> V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR = 1,
> @@ -756,18 +815,18 @@ enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type {
> V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE = 3,
> V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE = 4,
> };
> -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+3)
> +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_CODEC_CX2341X_BASE+3)
> enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type {
> V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF = 0,
> V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR = 1,
> };
> -#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+4)
> +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE (V4L2_CID_CODEC_CX2341X_BASE+4)
> enum v4l2_mpeg_cx2341x_video_temporal_filter_mode {
> V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL = 0,
> V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1,
> };
> -#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+5)
> -#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+6)
> +#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER (V4L2_CID_CODEC_CX2341X_BASE+5)
> +#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE (V4L2_CID_CODEC_CX2341X_BASE+6)
> enum v4l2_mpeg_cx2341x_video_median_filter_type {
> V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF = 0,
> V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR = 1,
> @@ -775,38 +834,38 @@ enum v4l2_mpeg_cx2341x_video_median_filter_type {
> V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3,
> V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG = 4,
> };
> -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+7)
> -#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+8)
> -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+9)
> -#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+10)
> -#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_MPEG_CX2341X_BASE+11)
> +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_CODEC_CX2341X_BASE+7)
> +#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_CODEC_CX2341X_BASE+8)
> +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_CODEC_CX2341X_BASE+9)
> +#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_CODEC_CX2341X_BASE+10)
> +#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_CODEC_CX2341X_BASE+11)
>
> /* MPEG-class control IDs specific to the Samsung MFC 5.1 driver as defined by V4L2 */
> -#define V4L2_CID_MPEG_MFC51_BASE (V4L2_CTRL_CLASS_MPEG | 0x1100)
> +#define V4L2_CID_CODEC_MFC51_BASE (V4L2_CTRL_CLASS_CODEC | 0x1100)
>
> -#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (V4L2_CID_MPEG_MFC51_BASE+0)
> -#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE (V4L2_CID_MPEG_MFC51_BASE+1)
> -#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE (V4L2_CID_MPEG_MFC51_BASE+2)
> +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (V4L2_CID_CODEC_MFC51_BASE+0)
> +#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE (V4L2_CID_CODEC_MFC51_BASE+1)
> +#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE (V4L2_CID_CODEC_MFC51_BASE+2)
> enum v4l2_mpeg_mfc51_video_frame_skip_mode {
> V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED = 0,
> V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT = 1,
> V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT = 2,
> };
> -#define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE (V4L2_CID_MPEG_MFC51_BASE+3)
> +#define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE (V4L2_CID_CODEC_MFC51_BASE+3)
> enum v4l2_mpeg_mfc51_video_force_frame_type {
> V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED = 0,
> V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_I_FRAME = 1,
> V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED = 2,
> };
> -#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING (V4L2_CID_MPEG_MFC51_BASE+4)
> -#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV (V4L2_CID_MPEG_MFC51_BASE+5)
> -#define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT (V4L2_CID_MPEG_MFC51_BASE+6)
> -#define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF (V4L2_CID_MPEG_MFC51_BASE+7)
> -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY (V4L2_CID_MPEG_MFC51_BASE+50)
> -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK (V4L2_CID_MPEG_MFC51_BASE+51)
> -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH (V4L2_CID_MPEG_MFC51_BASE+52)
> -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53)
> -#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54)
> +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING (V4L2_CID_CODEC_MFC51_BASE+4)
> +#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV (V4L2_CID_CODEC_MFC51_BASE+5)
> +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT (V4L2_CID_CODEC_MFC51_BASE+6)
> +#define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF (V4L2_CID_CODEC_MFC51_BASE+7)
> +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY (V4L2_CID_CODEC_MFC51_BASE+50)
> +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK (V4L2_CID_CODEC_MFC51_BASE+51)
> +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH (V4L2_CID_CODEC_MFC51_BASE+52)
> +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_CODEC_MFC51_BASE+53)
> +#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_CODEC_MFC51_BASE+54)
>
> /* Camera class control IDs */
>
> @@ -1049,6 +1108,7 @@ enum v4l2_jpeg_chroma_subsampling {
> #define V4L2_CID_TEST_PATTERN_GREENR (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 5)
> #define V4L2_CID_TEST_PATTERN_BLUE (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 6)
> #define V4L2_CID_TEST_PATTERN_GREENB (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 7)
> +#define V4L2_CID_UNIT_CELL_SIZE (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 8)
>
>
> /* Image processing controls */
> @@ -1142,4 +1202,468 @@ enum v4l2_detect_md_mode {
> #define V4L2_CID_DETECT_MD_THRESHOLD_GRID (V4L2_CID_DETECT_CLASS_BASE + 3)
> #define V4L2_CID_DETECT_MD_REGION_GRID (V4L2_CID_DETECT_CLASS_BASE + 4)
>
> +
> +/* Stateless CODECs controls */
> +#define V4L2_CID_CODEC_STATELESS_BASE (V4L2_CTRL_CLASS_CODEC_STATELESS | 0x900)
> +#define V4L2_CID_CODEC_STATELESS_CLASS (V4L2_CTRL_CLASS_CODEC_STATELESS | 1)
> +
> +#define V4L2_CID_STATELESS_H264_DECODE_MODE (V4L2_CID_CODEC_STATELESS_BASE + 0)
> +/**
> + * enum v4l2_stateless_h264_decode_mode - Decoding mode
> + *
> + * @V4L2_STATELESS_H264_DECODE_MODE_SLICE_BASED: indicates that decoding
> + * is performed one slice at a time. In this mode,
> + * V4L2_CID_STATELESS_H264_SLICE_PARAMS must contain the parsed slice
> + * parameters and the OUTPUT buffer must contain a single slice.
> + * V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF feature is used
> + * in order to support multislice frames.
> + * @V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED: indicates that
> + * decoding is performed per frame. The OUTPUT buffer must contain
> + * all slices and also both fields. This mode is typically supported
> + * by device drivers that are able to parse the slice(s) header(s)
> + * in hardware. When this mode is selected,
> + * V4L2_CID_STATELESS_H264_SLICE_PARAMS is not used.
> + */
> +enum v4l2_stateless_h264_decode_mode {
> + V4L2_STATELESS_H264_DECODE_MODE_SLICE_BASED,
> + V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
> +};
> +
> +#define V4L2_CID_STATELESS_H264_START_CODE (V4L2_CID_CODEC_STATELESS_BASE + 1)
> +/**
> + * enum v4l2_stateless_h264_start_code - Start code
> + *
> + * @V4L2_STATELESS_H264_START_CODE_NONE: slices are passed
> + * to the driver without any start code.
> + * @V4L2_STATELESS_H264_START_CODE_ANNEX_B: slices are passed
> + * to the driver with an Annex B start code prefix
> + * (legal start codes can be 3-bytes 0x000001 or 4-bytes 0x00000001).
> + * This mode is typically supported by device drivers that parse
> + * the start code in hardware.
> + */
> +enum v4l2_stateless_h264_start_code {
> + V4L2_STATELESS_H264_START_CODE_NONE,
> + V4L2_STATELESS_H264_START_CODE_ANNEX_B,
> +};
> +
> +#define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG 0x01
> +#define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG 0x02
> +#define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG 0x04
> +#define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG 0x08
> +#define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG 0x10
> +#define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG 0x20
> +
> +#define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE 0x01
> +#define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS 0x02
> +#define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO 0x04
> +#define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED 0x08
> +#define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY 0x10
> +#define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD 0x20
> +#define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE 0x40
> +
> +#define V4L2_H264_SPS_HAS_CHROMA_FORMAT(sps) \
> + ((sps)->profile_idc == 100 || (sps)->profile_idc == 110 || \
> + (sps)->profile_idc == 122 || (sps)->profile_idc == 244 || \
> + (sps)->profile_idc == 44 || (sps)->profile_idc == 83 || \
> + (sps)->profile_idc == 86 || (sps)->profile_idc == 118 || \
> + (sps)->profile_idc == 128 || (sps)->profile_idc == 138 || \
> + (sps)->profile_idc == 139 || (sps)->profile_idc == 134 || \
> + (sps)->profile_idc == 135)
> +
> +#define V4L2_CID_STATELESS_H264_SPS (V4L2_CID_CODEC_STATELESS_BASE + 2)
> +/**
> + * struct v4l2_ctrl_h264_sps - H264 sequence parameter set
> + *
> + * All the members on this sequence parameter set structure match the
> + * sequence parameter set syntax as specified by the H264 specification.
> + *
> + * @profile_idc: see H264 specification.
> + * @constraint_set_flags: see H264 specification.
> + * @level_idc: see H264 specification.
> + * @seq_parameter_set_id: see H264 specification.
> + * @chroma_format_idc: see H264 specification.
> + * @bit_depth_luma_minus8: see H264 specification.
> + * @bit_depth_chroma_minus8: see H264 specification.
> + * @log2_max_frame_num_minus4: see H264 specification.
> + * @pic_order_cnt_type: see H264 specification.
> + * @log2_max_pic_order_cnt_lsb_minus4: see H264 specification.
> + * @max_num_ref_frames: see H264 specification.
> + * @num_ref_frames_in_pic_order_cnt_cycle: see H264 specification.
> + * @offset_for_ref_frame: see H264 specification.
> + * @offset_for_non_ref_pic: see H264 specification.
> + * @offset_for_top_to_bottom_field: see H264 specification.
> + * @pic_width_in_mbs_minus1: see H264 specification.
> + * @pic_height_in_map_units_minus1: see H264 specification.
> + * @flags: see V4L2_H264_SPS_FLAG_{}.
> + */
> +struct v4l2_ctrl_h264_sps {
> + __u8 profile_idc;
> + __u8 constraint_set_flags;
> + __u8 level_idc;
> + __u8 seq_parameter_set_id;
> + __u8 chroma_format_idc;
> + __u8 bit_depth_luma_minus8;
> + __u8 bit_depth_chroma_minus8;
> + __u8 log2_max_frame_num_minus4;
> + __u8 pic_order_cnt_type;
> + __u8 log2_max_pic_order_cnt_lsb_minus4;
> + __u8 max_num_ref_frames;
> + __u8 num_ref_frames_in_pic_order_cnt_cycle;
> + __s32 offset_for_ref_frame[255];
> + __s32 offset_for_non_ref_pic;
> + __s32 offset_for_top_to_bottom_field;
> + __u16 pic_width_in_mbs_minus1;
> + __u16 pic_height_in_map_units_minus1;
> + __u32 flags;
> +};
> +
> +#define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE 0x0001
> +#define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT 0x0002
> +#define V4L2_H264_PPS_FLAG_WEIGHTED_PRED 0x0004
> +#define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT 0x0008
> +#define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED 0x0010
> +#define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT 0x0020
> +#define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE 0x0040
> +#define V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT 0x0080
> +
> +#define V4L2_CID_STATELESS_H264_PPS (V4L2_CID_CODEC_STATELESS_BASE + 3)
> +/**
> + * struct v4l2_ctrl_h264_pps - H264 picture parameter set
> + *
> + * Except where noted, all the members on this picture parameter set
> + * structure match the sequence parameter set syntax as specified
> + * by the H264 specification.
> + *
> + * In particular, V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT flag
> + * has a specific meaning. This flag should be set if a non-flat
> + * scaling matrix applies to the picture. In this case, applications
> + * are expected to use V4L2_CID_STATELESS_H264_SCALING_MATRIX,
> + * to pass the values of the non-flat matrices.
> + *
> + * @pic_parameter_set_id: see H264 specification.
> + * @seq_parameter_set_id: see H264 specification.
> + * @num_slice_groups_minus1: see H264 specification.
> + * @num_ref_idx_l0_default_active_minus1: see H264 specification.
> + * @num_ref_idx_l1_default_active_minus1: see H264 specification.
> + * @weighted_bipred_idc: see H264 specification.
> + * @pic_init_qp_minus26: see H264 specification.
> + * @pic_init_qs_minus26: see H264 specification.
> + * @chroma_qp_index_offset: see H264 specification.
> + * @second_chroma_qp_index_offset: see H264 specification.
> + * @flags: see V4L2_H264_PPS_FLAG_{}.
> + */
> +struct v4l2_ctrl_h264_pps {
> + __u8 pic_parameter_set_id;
> + __u8 seq_parameter_set_id;
> + __u8 num_slice_groups_minus1;
> + __u8 num_ref_idx_l0_default_active_minus1;
> + __u8 num_ref_idx_l1_default_active_minus1;
> + __u8 weighted_bipred_idc;
> + __s8 pic_init_qp_minus26;
> + __s8 pic_init_qs_minus26;
> + __s8 chroma_qp_index_offset;
> + __s8 second_chroma_qp_index_offset;
> + __u16 flags;
> +};
> +
> +#define V4L2_CID_STATELESS_H264_SCALING_MATRIX (V4L2_CID_CODEC_STATELESS_BASE + 4)
> +/**
> + * struct v4l2_ctrl_h264_scaling_matrix - H264 scaling matrices
> + *
> + * @scaling_list_4x4: scaling matrix after applying the inverse
> + * scanning process. Expected list order is Intra Y, Intra Cb,
> + * Intra Cr, Inter Y, Inter Cb, Inter Cr. The values on each
> + * scaling list are expected in raster scan order.
> + * @scaling_list_8x8: scaling matrix after applying the inverse
> + * scanning process. Expected list order is Intra Y, Inter Y,
> + * Intra Cb, Inter Cb, Intra Cr, Inter Cr. The values on each
> + * scaling list are expected in raster scan order.
> + *
> + * Note that the list order is different for the 4x4 and 8x8
> + * matrices as per the H264 specification, see table 7-2 "Assignment
> + * of mnemonic names to scaling list indices and specification of
> + * fall-back rule".
> + */
> +struct v4l2_ctrl_h264_scaling_matrix {
> + __u8 scaling_list_4x4[6][16];
> + __u8 scaling_list_8x8[6][64];
> +};
> +
> +struct v4l2_h264_weight_factors {
> + __s16 luma_weight[32];
> + __s16 luma_offset[32];
> + __s16 chroma_weight[32][2];
> + __s16 chroma_offset[32][2];
> +};
> +
> +#define V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(pps, slice) \
> + ((((pps)->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && \
> + ((slice)->slice_type == V4L2_H264_SLICE_TYPE_P || \
> + (slice)->slice_type == V4L2_H264_SLICE_TYPE_SP)) || \
> + ((pps)->weighted_bipred_idc == 1 && \
> + (slice)->slice_type == V4L2_H264_SLICE_TYPE_B))
> +
> +#define V4L2_CID_STATELESS_H264_PRED_WEIGHTS (V4L2_CID_CODEC_STATELESS_BASE + 5)
> +/**
> + * struct v4l2_ctrl_h264_pred_weights - Prediction weight table
> + *
> + * Prediction weight table, which matches the syntax specified
> + * by the H264 specification.
> + *
> + * @luma_log2_weight_denom: see H264 specification.
> + * @chroma_log2_weight_denom: see H264 specification.
> + * @weight_factors: luma and chroma weight factors.
> + */
> +struct v4l2_ctrl_h264_pred_weights {
> + __u16 luma_log2_weight_denom;
> + __u16 chroma_log2_weight_denom;
> + struct v4l2_h264_weight_factors weight_factors[2];
> +};
> +
> +#define V4L2_H264_SLICE_TYPE_P 0
> +#define V4L2_H264_SLICE_TYPE_B 1
> +#define V4L2_H264_SLICE_TYPE_I 2
> +#define V4L2_H264_SLICE_TYPE_SP 3
> +#define V4L2_H264_SLICE_TYPE_SI 4
> +
> +#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x01
> +#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x02
> +
> +#define V4L2_H264_TOP_FIELD_REF 0x1
> +#define V4L2_H264_BOTTOM_FIELD_REF 0x2
> +#define V4L2_H264_FRAME_REF 0x3
> +
> +/**
> + * struct v4l2_h264_reference - H264 picture reference
> + *
> + * @fields: indicates how the picture is referenced.
> + * Valid values are V4L2_H264_{}_REF.
> + * @index: index into v4l2_ctrl_h264_decode_params.dpb[].
> + */
> +struct v4l2_h264_reference {
> + __u8 fields;
> + __u8 index;
> +};
> +
> +/*
> + * Maximum DPB size, as specified by section 'A.3.1 Level limits
> + * common to the Baseline, Main, and Extended profiles'.
> + */
> +#define V4L2_H264_NUM_DPB_ENTRIES 16
> +#define V4L2_H264_REF_LIST_LEN (2 * V4L2_H264_NUM_DPB_ENTRIES)
> +
> +#define V4L2_CID_STATELESS_H264_SLICE_PARAMS (V4L2_CID_CODEC_STATELESS_BASE + 6)
> +/**
> + * struct v4l2_ctrl_h264_slice_params - H264 slice parameters
> + *
> + * This structure holds the H264 syntax elements that are specified
> + * as non-invariant for the slices in a given frame.
> + *
> + * Slice invariant syntax elements are contained in struct
> + * v4l2_ctrl_h264_decode_params. This is done to reduce the API surface
> + * on frame-based decoders, where slice header parsing is done by the
> + * hardware.
> + *
> + * Slice invariant syntax elements are specified in specification section
> + * "7.4.3 Slice header semantics".
> + *
> + * Except where noted, the members on this struct match the slice header syntax.
> + *
> + * @header_bit_size: offset in bits to slice_data() from the beginning of this slice.
> + * @first_mb_in_slice: see H264 specification.
> + * @slice_type: see H264 specification.
> + * @colour_plane_id: see H264 specification.
> + * @redundant_pic_cnt: see H264 specification.
> + * @cabac_init_idc: see H264 specification.
> + * @slice_qp_delta: see H264 specification.
> + * @slice_qs_delta: see H264 specification.
> + * @disable_deblocking_filter_idc: see H264 specification.
> + * @slice_alpha_c0_offset_div2: see H264 specification.
> + * @slice_beta_offset_div2: see H264 specification.
> + * @num_ref_idx_l0_active_minus1: see H264 specification.
> + * @num_ref_idx_l1_active_minus1: see H264 specification.
> + * @reserved: padding field. Should be zeroed by applications.
> + * @ref_pic_list0: reference picture list 0 after applying the per-slice modifications.
> + * @ref_pic_list1: reference picture list 1 after applying the per-slice modifications.
> + * @flags: see V4L2_H264_SLICE_FLAG_{}.
> + */
> +struct v4l2_ctrl_h264_slice_params {
> + __u32 header_bit_size;
> + __u32 first_mb_in_slice;
> + __u8 slice_type;
> + __u8 colour_plane_id;
> + __u8 redundant_pic_cnt;
> + __u8 cabac_init_idc;
> + __s8 slice_qp_delta;
> + __s8 slice_qs_delta;
> + __u8 disable_deblocking_filter_idc;
> + __s8 slice_alpha_c0_offset_div2;
> + __s8 slice_beta_offset_div2;
> + __u8 num_ref_idx_l0_active_minus1;
> + __u8 num_ref_idx_l1_active_minus1;
> +
> + __u8 reserved;
> +
> + struct v4l2_h264_reference ref_pic_list0[V4L2_H264_REF_LIST_LEN];
> + struct v4l2_h264_reference ref_pic_list1[V4L2_H264_REF_LIST_LEN];
> +
> + __u32 flags;
> +};
> +
> +#define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01
> +#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02
> +#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04
> +#define V4L2_H264_DPB_ENTRY_FLAG_FIELD 0x08
> +
> +/**
> + * struct v4l2_h264_dpb_entry - H264 decoded picture buffer entry
> + *
> + * @reference_ts: timestamp of the V4L2 capture buffer to use as reference.
> + * The timestamp refers to the timestamp field in struct v4l2_buffer.
> + * Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64.
> + * @pic_num: matches PicNum variable assigned during the reference
> + * picture lists construction process.
> + * @frame_num: frame identifier which matches frame_num syntax element.
> + * @fields: indicates how the DPB entry is referenced. Valid values are
> + * V4L2_H264_{}_REF.
> + * @reserved: padding field. Should be zeroed by applications.
> + * @top_field_order_cnt: matches TopFieldOrderCnt picture value.
> + * @bottom_field_order_cnt: matches BottomFieldOrderCnt picture value.
> + * Note that picture field is indicated by v4l2_buffer.field.
> + * @flags: see V4L2_H264_DPB_ENTRY_FLAG_{}.
> + */
> +struct v4l2_h264_dpb_entry {
> + __u64 reference_ts;
> + __u32 pic_num;
> + __u16 frame_num;
> + __u8 fields;
> + __u8 reserved[5];
> + __s32 top_field_order_cnt;
> + __s32 bottom_field_order_cnt;
> + __u32 flags;
> +};
> +
> +#define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01
> +#define V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC 0x02
> +#define V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD 0x04
> +
> +#define V4L2_CID_STATELESS_H264_DECODE_PARAMS (V4L2_CID_CODEC_STATELESS_BASE + 7)
> +/**
> + * struct v4l2_ctrl_h264_decode_params - H264 decoding parameters
> + *
> + * @dpb: decoded picture buffer.
> + * @nal_ref_idc: slice header syntax element.
> + * @frame_num: slice header syntax element.
> + * @top_field_order_cnt: matches TopFieldOrderCnt picture value.
> + * @bottom_field_order_cnt: matches BottomFieldOrderCnt picture value.
> + * Note that picture field is indicated by v4l2_buffer.field.
> + * @idr_pic_id: slice header syntax element.
> + * @pic_order_cnt_lsb: slice header syntax element.
> + * @delta_pic_order_cnt_bottom: slice header syntax element.
> + * @delta_pic_order_cnt0: slice header syntax element.
> + * @delta_pic_order_cnt1: slice header syntax element.
> + * @dec_ref_pic_marking_bit_size: size in bits of dec_ref_pic_marking()
> + * syntax element.
> + * @pic_order_cnt_bit_size: size in bits of pic order count syntax.
> + * @slice_group_change_cycle: slice header syntax element.
> + * @reserved: padding field. Should be zeroed by applications.
> + * @flags: see V4L2_H264_DECODE_PARAM_FLAG_{}.
> + */
> +struct v4l2_ctrl_h264_decode_params {
> + struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES];
> + __u16 nal_ref_idc;
> + __u16 frame_num;
> + __s32 top_field_order_cnt;
> + __s32 bottom_field_order_cnt;
> + __u16 idr_pic_id;
> + __u16 pic_order_cnt_lsb;
> + __s32 delta_pic_order_cnt_bottom;
> + __s32 delta_pic_order_cnt0;
> + __s32 delta_pic_order_cnt1;
> + __u32 dec_ref_pic_marking_bit_size;
> + __u32 pic_order_cnt_bit_size;
> + __u32 slice_group_change_cycle;
> +
> + __u32 reserved;
> + __u32 flags;
> +};
> +
> +
> +/* Stateless FWHT control, used by the vicodec driver */
> +
> +/* Current FWHT version */
> +#define V4L2_FWHT_VERSION 3
> +
> +/* Set if this is an interlaced format */
> +#define V4L2_FWHT_FL_IS_INTERLACED BIT(0)
> +/* Set if this is a bottom-first (NTSC) interlaced format */
> +#define V4L2_FWHT_FL_IS_BOTTOM_FIRST BIT(1)
> +/* Set if each 'frame' contains just one field */
> +#define V4L2_FWHT_FL_IS_ALTERNATE BIT(2)
> +/*
> + * If V4L2_FWHT_FL_IS_ALTERNATE was set, then this is set if this
> + * 'frame' is the bottom field, else it is the top field.
> + */
> +#define V4L2_FWHT_FL_IS_BOTTOM_FIELD BIT(3)
> +/* Set if the Y' plane is uncompressed */
> +#define V4L2_FWHT_FL_LUMA_IS_UNCOMPRESSED BIT(4)
> +/* Set if the Cb plane is uncompressed */
> +#define V4L2_FWHT_FL_CB_IS_UNCOMPRESSED BIT(5)
> +/* Set if the Cr plane is uncompressed */
> +#define V4L2_FWHT_FL_CR_IS_UNCOMPRESSED BIT(6)
> +/* Set if the chroma plane is full height, if cleared it is half height */
> +#define V4L2_FWHT_FL_CHROMA_FULL_HEIGHT BIT(7)
> +/* Set if the chroma plane is full width, if cleared it is half width */
> +#define V4L2_FWHT_FL_CHROMA_FULL_WIDTH BIT(8)
> +/* Set if the alpha plane is uncompressed */
> +#define V4L2_FWHT_FL_ALPHA_IS_UNCOMPRESSED BIT(9)
> +/* Set if this is an I Frame */
> +#define V4L2_FWHT_FL_I_FRAME BIT(10)
> +
> +/* A 4-values flag - the number of components - 1 */
> +#define V4L2_FWHT_FL_COMPONENTS_NUM_MSK GENMASK(18, 16)
> +#define V4L2_FWHT_FL_COMPONENTS_NUM_OFFSET 16
> +
> +/* A 4-values flag - the pixel encoding type */
> +#define V4L2_FWHT_FL_PIXENC_MSK GENMASK(20, 19)
> +#define V4L2_FWHT_FL_PIXENC_OFFSET 19
> +#define V4L2_FWHT_FL_PIXENC_YUV (1 << V4L2_FWHT_FL_PIXENC_OFFSET)
> +#define V4L2_FWHT_FL_PIXENC_RGB (2 << V4L2_FWHT_FL_PIXENC_OFFSET)
> +#define V4L2_FWHT_FL_PIXENC_HSV (3 << V4L2_FWHT_FL_PIXENC_OFFSET)
> +
> +#define V4L2_CID_STATELESS_FWHT_PARAMS (V4L2_CID_CODEC_STATELESS_BASE + 100)
> +/**
> + * struct v4l2_ctrl_fwht_params - FWHT parameters
> + *
> + * @backward_ref_ts: timestamp of the V4L2 capture buffer to use as reference.
> + * The timestamp refers to the timestamp field in struct v4l2_buffer.
> + * Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64.
> + * @version: must be V4L2_FWHT_VERSION.
> + * @width: width of frame.
> + * @height: height of frame.
> + * @flags: FWHT flags (see V4L2_FWHT_FL_*).
> + * @colorspace: the colorspace (enum v4l2_colorspace).
> + * @xfer_func: the transfer function (enum v4l2_xfer_func).
> + * @ycbcr_enc: the Y'CbCr encoding (enum v4l2_ycbcr_encoding).
> + * @quantization: the quantization (enum v4l2_quantization).
> + */
> +struct v4l2_ctrl_fwht_params {
> + __u64 backward_ref_ts;
> + __u32 version;
> + __u32 width;
> + __u32 height;
> + __u32 flags;
> + __u32 colorspace;
> + __u32 xfer_func;
> + __u32 ycbcr_enc;
> + __u32 quantization;
> +};
> +
> +/* MPEG-compression definitions kept for backwards compatibility */
> +#define V4L2_CTRL_CLASS_MPEG V4L2_CTRL_CLASS_CODEC
> +#define V4L2_CID_MPEG_CLASS V4L2_CID_CODEC_CLASS
> +#define V4L2_CID_MPEG_BASE V4L2_CID_CODEC_BASE
> +#define V4L2_CID_MPEG_CX2341X_BASE V4L2_CID_CODEC_CX2341X_BASE
> +#define V4L2_CID_MPEG_MFC51_BASE V4L2_CID_CODEC_MFC51_BASE
> +
> #endif
> diff --git a/include/linux/v4l2-mediabus.h b/include/linux/v4l2-mediabus.h
> index 0fb5bfbec871..846dadfbfc64 100644
> --- a/include/linux/v4l2-mediabus.h
> +++ b/include/linux/v4l2-mediabus.h
> @@ -16,6 +16,8 @@
> #include <linux/types.h>
> #include <linux/videodev2.h>
>
> +#define V4L2_MBUS_FRAMEFMT_SET_CSC 0x0001
> +
> /**
> * struct v4l2_mbus_framefmt - frame format on the media bus
> * @width: image width
> @@ -24,8 +26,11 @@
> * @field: used interlacing type (from enum v4l2_field)
> * @colorspace: colorspace of the data (from enum v4l2_colorspace)
> * @ycbcr_enc: YCbCr encoding of the data (from enum v4l2_ycbcr_encoding)
> + * @hsv_enc: HSV encoding of the data (from enum v4l2_hsv_encoding)
> * @quantization: quantization of the data (from enum v4l2_quantization)
> * @xfer_func: transfer function of the data (from enum v4l2_xfer_func)
> + * @flags: flags (V4L2_MBUS_FRAMEFMT_*)
> + * @reserved: reserved bytes that can be later used
> */
> struct v4l2_mbus_framefmt {
> __u32 width;
> @@ -33,10 +38,16 @@ struct v4l2_mbus_framefmt {
> __u32 code;
> __u32 field;
> __u32 colorspace;
> - __u16 ycbcr_enc;
> + union {
> + /* enum v4l2_ycbcr_encoding */
> + __u16 ycbcr_enc;
> + /* enum v4l2_hsv_encoding */
> + __u16 hsv_enc;
> + };
> __u16 quantization;
> __u16 xfer_func;
> - __u16 reserved[11];
> + __u16 flags;
> + __u16 reserved[10];
> };
>
> /*
> diff --git a/include/linux/v4l2-subdev.h b/include/linux/v4l2-subdev.h
> index 03970ce30741..a38454d9e0f5 100644
> --- a/include/linux/v4l2-subdev.h
> +++ b/include/linux/v4l2-subdev.h
> @@ -65,19 +65,27 @@ struct v4l2_subdev_crop {
> __u32 reserved[8];
> };
>
> +#define V4L2_SUBDEV_MBUS_CODE_CSC_COLORSPACE 0x00000001
> +#define V4L2_SUBDEV_MBUS_CODE_CSC_XFER_FUNC 0x00000002
> +#define V4L2_SUBDEV_MBUS_CODE_CSC_YCBCR_ENC 0x00000004
> +#define V4L2_SUBDEV_MBUS_CODE_CSC_HSV_ENC V4L2_SUBDEV_MBUS_CODE_CSC_YCBCR_ENC
> +#define V4L2_SUBDEV_MBUS_CODE_CSC_QUANTIZATION 0x00000008
> +
> /**
> * struct v4l2_subdev_mbus_code_enum - Media bus format enumeration
> * @pad: pad number, as reported by the media API
> * @index: format index during enumeration
> * @code: format code (MEDIA_BUS_FMT_ definitions)
> * @which: format type (from enum v4l2_subdev_format_whence)
> + * @flags: flags set by the driver, (V4L2_SUBDEV_MBUS_CODE_*)
> */
> struct v4l2_subdev_mbus_code_enum {
> __u32 pad;
> __u32 index;
> __u32 code;
> __u32 which;
> - __u32 reserved[8];
> + __u32 flags;
> + __u32 reserved[7];
> };
>
> /**
> @@ -155,9 +163,25 @@ struct v4l2_subdev_selection {
> __u32 reserved[8];
> };
>
> +/**
> + * struct v4l2_subdev_capability - subdev capabilities
> + * @version: the driver versioning number
> + * @capabilities: the subdev capabilities, see V4L2_SUBDEV_CAP_*
> + * @reserved: for future use, set to zero for now
> + */
> +struct v4l2_subdev_capability {
> + __u32 version;
> + __u32 capabilities;
> + __u32 reserved[14];
> +};
> +
> +/* The v4l2 sub-device video device node is registered in read-only mode. */
> +#define V4L2_SUBDEV_CAP_RO_SUBDEV 0x00000001
> +
> /* Backwards compatibility define --- to be removed */
> #define v4l2_subdev_edid v4l2_edid
>
> +#define VIDIOC_SUBDEV_QUERYCAP _IOR('V', 0, struct v4l2_subdev_capability)
> #define VIDIOC_SUBDEV_G_FMT _IOWR('V', 4, struct v4l2_subdev_format)
> #define VIDIOC_SUBDEV_S_FMT _IOWR('V', 5, struct v4l2_subdev_format)
> #define VIDIOC_SUBDEV_G_FRAME_INTERVAL _IOWR('V', 21, struct v4l2_subdev_frame_interval)
> diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
> index c70d766187a0..f54075406e47 100644
> --- a/include/linux/videodev2.h
> +++ b/include/linux/videodev2.h
> @@ -169,6 +169,8 @@ enum v4l2_buf_type {
> || (type) == V4L2_BUF_TYPE_SDR_OUTPUT \
> || (type) == V4L2_BUF_TYPE_META_OUTPUT)
>
> +#define V4L2_TYPE_IS_CAPTURE(type) (!V4L2_TYPE_IS_OUTPUT(type))
> +
> enum v4l2_tuner_type {
> V4L2_TUNER_RADIO = 1,
> V4L2_TUNER_ANALOG_TV = 2,
> @@ -217,9 +219,7 @@ enum v4l2_colorspace {
> V4L2_COLORSPACE_470_SYSTEM_M = 5,
>
> /*
> - * EBU Tech 3213 PAL/SECAM colorspace. This only makes sense when
> - * dealing with really old PAL/SECAM recordings. Superseded by
> - * SMPTE 170M.
> + * EBU Tech 3213 PAL/SECAM colorspace.
> */
> V4L2_COLORSPACE_470_SYSTEM_BG = 6,
>
> @@ -367,9 +367,9 @@ enum v4l2_hsv_encoding {
>
> enum v4l2_quantization {
> /*
> - * The default for R'G'B' quantization is always full range, except
> - * for the BT2020 colorspace. For Y'CbCr the quantization is always
> - * limited range, except for COLORSPACE_JPEG: this is full range.
> + * The default for R'G'B' quantization is always full range.
> + * For Y'CbCr the quantization is always limited range, except
> + * for COLORSPACE_JPEG: this is full range.
> */
> V4L2_QUANTIZATION_DEFAULT = 0,
> V4L2_QUANTIZATION_FULL_RANGE = 1,
> @@ -378,14 +378,13 @@ enum v4l2_quantization {
>
> /*
> * Determine how QUANTIZATION_DEFAULT should map to a proper quantization.
> - * This depends on whether the image is RGB or not, the colorspace and the
> - * Y'CbCr encoding.
> + * This depends on whether the image is RGB or not, the colorspace.
> + * The Y'CbCr encoding is not used anymore, but is still there for backwards
> + * compatibility.
> */
> #define V4L2_MAP_QUANTIZATION_DEFAULT(is_rgb_or_hsv, colsp, ycbcr_enc) \
> - (((is_rgb_or_hsv) && (colsp) == V4L2_COLORSPACE_BT2020) ? \
> - V4L2_QUANTIZATION_LIM_RANGE : \
> - (((is_rgb_or_hsv) || (colsp) == V4L2_COLORSPACE_JPEG) ? \
> - V4L2_QUANTIZATION_FULL_RANGE : V4L2_QUANTIZATION_LIM_RANGE))
> + (((is_rgb_or_hsv) || (colsp) == V4L2_COLORSPACE_JPEG) ? \
> + V4L2_QUANTIZATION_FULL_RANGE : V4L2_QUANTIZATION_LIM_RANGE)
>
> /*
> * Deprecated names for opRGB colorspace (IEC 61966-2-5)
> @@ -416,6 +415,11 @@ struct v4l2_fract {
> __u32 denominator;
> };
>
> +struct v4l2_area {
> + __u32 width;
> + __u32 height;
> +};
> +
> /**
> * struct v4l2_capability - Describes V4L2 device caps returned by VIDIOC_QUERYCAP
> *
> @@ -505,7 +509,7 @@ struct v4l2_pix_format {
>
> /* Pixel format FOURCC depth Description */
>
> -/* RGB formats */
> +/* RGB formats (1 or 2 bytes per pixel) */
> #define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R', 'G', 'B', '1') /* 8 RGB-3-3-2 */
> #define V4L2_PIX_FMT_RGB444 v4l2_fourcc('R', '4', '4', '4') /* 16 xxxxrrrr ggggbbbb */
> #define V4L2_PIX_FMT_ARGB444 v4l2_fourcc('A', 'R', '1', '2') /* 16 aaaarrrr ggggbbbb */
> @@ -514,12 +518,6 @@ struct v4l2_pix_format {
> #define V4L2_PIX_FMT_RGBX444 v4l2_fourcc('R', 'X', '1', '2') /* 16 rrrrgggg bbbbxxxx */
> #define V4L2_PIX_FMT_ABGR444 v4l2_fourcc('A', 'B', '1', '2') /* 16 aaaabbbb ggggrrrr */
> #define V4L2_PIX_FMT_XBGR444 v4l2_fourcc('X', 'B', '1', '2') /* 16 xxxxbbbb ggggrrrr */
> -
> -/*
> - * Originally this had 'BA12' as fourcc, but this clashed with the older
> - * V4L2_PIX_FMT_SGRBG12 which inexplicably used that same fourcc.
> - * So use 'GA12' instead for V4L2_PIX_FMT_BGRA444.
> - */
> #define V4L2_PIX_FMT_BGRA444 v4l2_fourcc('G', 'A', '1', '2') /* 16 bbbbgggg rrrraaaa */
> #define V4L2_PIX_FMT_BGRX444 v4l2_fourcc('B', 'X', '1', '2') /* 16 bbbbgggg rrrrxxxx */
> #define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R', 'G', 'B', 'O') /* 16 RGB-5-5-5 */
> @@ -536,6 +534,8 @@ struct v4l2_pix_format {
> #define V4L2_PIX_FMT_ARGB555X v4l2_fourcc_be('A', 'R', '1', '5') /* 16 ARGB-5-5-5 BE */
> #define V4L2_PIX_FMT_XRGB555X v4l2_fourcc_be('X', 'R', '1', '5') /* 16 XRGB-5-5-5 BE */
> #define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16 RGB-5-6-5 BE */
> +
> +/* RGB formats (3 or 4 bytes per pixel) */
> #define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H') /* 18 BGR-6-6-6 */
> #define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') /* 24 BGR-8-8-8 */
> #define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') /* 24 RGB-8-8-8 */
> @@ -556,6 +556,7 @@ struct v4l2_pix_format {
> #define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ') /* 6 Greyscale */
> #define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ') /* 10 Greyscale */
> #define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') /* 12 Greyscale */
> +#define V4L2_PIX_FMT_Y14 v4l2_fourcc('Y', '1', '4', ' ') /* 14 Greyscale */
> #define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */
> #define V4L2_PIX_FMT_Y16_BE v4l2_fourcc_be('Y', '1', '6', ' ') /* 16 Greyscale BE */
>
> @@ -584,8 +585,6 @@ struct v4l2_pix_format {
> #define V4L2_PIX_FMT_XYUV32 v4l2_fourcc('X', 'Y', 'U', 'V') /* 32 XYUV-8-8-8-8 */
> #define V4L2_PIX_FMT_VUYA32 v4l2_fourcc('V', 'U', 'Y', 'A') /* 32 VUYA-8-8-8-8 */
> #define V4L2_PIX_FMT_VUYX32 v4l2_fourcc('V', 'U', 'Y', 'X') /* 32 VUYX-8-8-8-8 */
> -#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */
> -#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */
> #define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') /* 12 YUV 4:2:0 2 lines y, 1 line uv interleaved */
>
> /* two planes -- one Y, one Cr + Cb interleaved */
> @@ -595,6 +594,7 @@ struct v4l2_pix_format {
> #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */
> #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */
> #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */
> +#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */
>
> /* two non contiguous planes - one Y, one Cr + Cb interleaved */
> #define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */
> @@ -653,6 +653,10 @@ struct v4l2_pix_format {
> #define V4L2_PIX_FMT_SGBRG12P v4l2_fourcc('p', 'G', 'C', 'C')
> #define V4L2_PIX_FMT_SGRBG12P v4l2_fourcc('p', 'g', 'C', 'C')
> #define V4L2_PIX_FMT_SRGGB12P v4l2_fourcc('p', 'R', 'C', 'C')
> +#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.. GRGR.. */
> +#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.. RGRG.. */
> +#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('G', 'R', '1', '4') /* 14 GRGR.. BGBG.. */
> +#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.. GBGB.. */
> /* 14bit raw bayer packed, 7 bytes for every 4 pixels */
> #define V4L2_PIX_FMT_SBGGR14P v4l2_fourcc('p', 'B', 'E', 'E')
> #define V4L2_PIX_FMT_SGBRG14P v4l2_fourcc('p', 'G', 'E', 'E')
> @@ -688,6 +692,7 @@ struct v4l2_pix_format {
> #define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC aka H.265 */
> #define V4L2_PIX_FMT_FWHT v4l2_fourcc('F', 'W', 'H', 'T') /* Fast Walsh Hadamard Transform (vicodec) */
> #define V4L2_PIX_FMT_FWHT_STATELESS v4l2_fourcc('S', 'F', 'W', 'H') /* Stateless FWHT (vicodec) */
> +#define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */
>
> /* Vendor-specific formats */
> #define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */
> @@ -723,6 +728,7 @@ struct v4l2_pix_format {
> #define V4L2_PIX_FMT_INZI v4l2_fourcc('I', 'N', 'Z', 'I') /* Intel Planar Greyscale 10-bit and Depth 16-bit */
> #define V4L2_PIX_FMT_SUNXI_TILED_NV12 v4l2_fourcc('S', 'T', '1', '2') /* Sunxi Tiled NV12 Format */
> #define V4L2_PIX_FMT_CNF4 v4l2_fourcc('C', 'N', 'F', '4') /* Intel 4-bit packed depth confidence information */
> +#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* BTTV 8-bit dithered RGB */
>
> /* 10bit raw bayer packed, 32 bytes for every 25 pixels, last LSB 6 bits unused */
> #define V4L2_PIX_FMT_IPU3_SBGGR10 v4l2_fourcc('i', 'p', '3', 'b') /* IPU3 packed 10-bit BGGR bayer */
> @@ -751,18 +757,20 @@ struct v4l2_pix_format {
> #define V4L2_META_FMT_VSP1_HGT v4l2_fourcc('V', 'S', 'P', 'T') /* R-Car VSP1 2-D Histogram */
> #define V4L2_META_FMT_UVC v4l2_fourcc('U', 'V', 'C', 'H') /* UVC Payload Header metadata */
> #define V4L2_META_FMT_D4XX v4l2_fourcc('D', '4', 'X', 'X') /* D4XX Payload Header metadata */
> +#define V4L2_META_FMT_VIVID v4l2_fourcc('V', 'I', 'V', 'D') /* Vivid Metadata */
> #define V4L2_META_FMT_SENSOR_DATA v4l2_fourcc('S', 'E', 'N', 'S') /* Sensor Ancillary metadata */
> #define V4L2_META_FMT_BCM2835_ISP_STATS v4l2_fourcc('B', 'S', 'T', 'A') /* BCM2835 ISP image statistics output */
>
> /* Vendor specific - used for RK_ISP1 camera sub-system */
> -#define V4L2_META_FMT_RK_ISP1_PARAMS v4l2_fourcc('R', 'K', '1', 'P') /* Rockchip ISP1 params */
> -#define V4L2_META_FMT_RK_ISP1_STAT_3A v4l2_fourcc('R', 'K', '1', 'S') /* Rockchip ISP1 3A statistics */
> +#define V4L2_META_FMT_RK_ISP1_PARAMS v4l2_fourcc('R', 'K', '1', 'P') /* Rockchip ISP1 3A Parameters */
> +#define V4L2_META_FMT_RK_ISP1_STAT_3A v4l2_fourcc('R', 'K', '1', 'S') /* Rockchip ISP1 3A Statistics */
>
> /* priv field value to indicates that subsequent fields are valid. */
> #define V4L2_PIX_FMT_PRIV_MAGIC 0xfeedcafe
>
> /* Flags */
> #define V4L2_PIX_FMT_FLAG_PREMUL_ALPHA 0x00000001
> +#define V4L2_PIX_FMT_FLAG_SET_CSC 0x00000002
>
> /*
> * F O R M A T E N U M E R A T I O N
> @@ -781,6 +789,12 @@ struct v4l2_fmtdesc {
> #define V4L2_FMT_FLAG_EMULATED 0x0002
> #define V4L2_FMT_FLAG_CONTINUOUS_BYTESTREAM 0x0004
> #define V4L2_FMT_FLAG_DYN_RESOLUTION 0x0008
> +#define V4L2_FMT_FLAG_ENC_CAP_FRAME_INTERVAL 0x0010
> +#define V4L2_FMT_FLAG_CSC_COLORSPACE 0x0020
> +#define V4L2_FMT_FLAG_CSC_XFER_FUNC 0x0040
> +#define V4L2_FMT_FLAG_CSC_YCBCR_ENC 0x0080
> +#define V4L2_FMT_FLAG_CSC_HSV_ENC V4L2_FMT_FLAG_CSC_YCBCR_ENC
> +#define V4L2_FMT_FLAG_CSC_QUANTIZATION 0x0100
>
> /* Frame Size and frame rate enumeration */
> /*
> @@ -909,6 +923,8 @@ struct v4l2_jpegcompression {
> /*
> * M E M O R Y - M A P P I N G B U F F E R S
> */
> +
> +
> struct v4l2_requestbuffers {
> __u32 count;
> __u32 type; /* enum v4l2_buf_type */
> @@ -918,11 +934,13 @@ struct v4l2_requestbuffers {
> };
>
> /* capabilities for struct v4l2_requestbuffers and v4l2_create_buffers */
> -#define V4L2_BUF_CAP_SUPPORTS_MMAP (1 << 0)
> -#define V4L2_BUF_CAP_SUPPORTS_USERPTR (1 << 1)
> -#define V4L2_BUF_CAP_SUPPORTS_DMABUF (1 << 2)
> -#define V4L2_BUF_CAP_SUPPORTS_REQUESTS (1 << 3)
> -#define V4L2_BUF_CAP_SUPPORTS_ORPHANED_BUFS (1 << 4)
> +#define V4L2_BUF_CAP_SUPPORTS_MMAP (1 << 0)
> +#define V4L2_BUF_CAP_SUPPORTS_USERPTR (1 << 1)
> +#define V4L2_BUF_CAP_SUPPORTS_DMABUF (1 << 2)
> +#define V4L2_BUF_CAP_SUPPORTS_REQUESTS (1 << 3)
> +#define V4L2_BUF_CAP_SUPPORTS_ORPHANED_BUFS (1 << 4)
> +#define V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF (1 << 5)
> +#define V4L2_BUF_CAP_SUPPORTS_MMAP_CACHE_HINTS (1 << 6)
>
> /**
> * struct v4l2_plane - plane info for multi-planar buffers
> @@ -1044,6 +1062,8 @@ static __inline__ __u64 v4l2_timeval_to_ns(const struct timeval *tv)
> #define V4L2_BUF_FLAG_IN_REQUEST 0x00000080
> /* timecode field is valid */
> #define V4L2_BUF_FLAG_TIMECODE 0x00000100
> +/* Don't return the capture buffer until OUTPUT timestamp changes */
> +#define V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF 0x00000200
> /* Buffer is prepared for queuing */
> #define V4L2_BUF_FLAG_PREPARED 0x00000400
> /* Cache handling flags */
> @@ -1211,6 +1231,10 @@ struct v4l2_selection {
>
> typedef __u64 v4l2_std_id;
>
> +/*
> + * Attention: Keep the V4L2_STD_* bit definitions in sync with
> + * include/dt-bindings/display/sdtv-standards.h SDTV_STD_* bit definitions.
> + */
> /* one bit for each */
> #define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001)
> #define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002)
> @@ -1678,6 +1702,14 @@ struct v4l2_ext_control {
> __u8 *p_u8;
> __u16 *p_u16;
> __u32 *p_u32;
> + struct v4l2_area *p_area;
> + struct v4l2_ctrl_h264_sps *p_h264_sps;
> + struct v4l2_ctrl_h264_pps *p_h264_pps;
> + struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix;
> + struct v4l2_ctrl_h264_pred_weights *p_h264_pred_weights;
> + struct v4l2_ctrl_h264_slice_params *p_h264_slice_params;
> + struct v4l2_ctrl_h264_decode_params *p_h264_decode_params;
> + struct v4l2_ctrl_fwht_params *p_fwht_params;
> void *ptr;
> };
> } __attribute__ ((packed));
> @@ -1719,6 +1751,16 @@ enum v4l2_ctrl_type {
> V4L2_CTRL_TYPE_U8 = 0x0100,
> V4L2_CTRL_TYPE_U16 = 0x0101,
> V4L2_CTRL_TYPE_U32 = 0x0102,
> + V4L2_CTRL_TYPE_AREA = 0x0106,
> +
> + V4L2_CTRL_TYPE_H264_SPS = 0x0200,
> + V4L2_CTRL_TYPE_H264_PPS = 0x0201,
> + V4L2_CTRL_TYPE_H264_SCALING_MATRIX = 0x0202,
> + V4L2_CTRL_TYPE_H264_SLICE_PARAMS = 0x0203,
> + V4L2_CTRL_TYPE_H264_DECODE_PARAMS = 0x0204,
> + V4L2_CTRL_TYPE_H264_PRED_WEIGHTS = 0x0205,
> +
> + V4L2_CTRL_TYPE_FWHT_PARAMS = 0x0220,
> };
>
> /* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */
> @@ -1974,6 +2016,7 @@ struct v4l2_encoder_cmd {
> #define V4L2_DEC_CMD_STOP (1)
> #define V4L2_DEC_CMD_PAUSE (2)
> #define V4L2_DEC_CMD_RESUME (3)
> +#define V4L2_DEC_CMD_FLUSH (4)
>
> /* Flags for V4L2_DEC_CMD_START */
> #define V4L2_DEC_CMD_START_MUTE_AUDIO (1 << 0)
>
--
Regards
--
Kieran
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